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SRAM memory cell leakage reduction design techniques in 65nm low power PD-SOI CMOS

SRAM memory cell leakage reduction design techniques in 65nm...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Olivier Thomas Marc Belleville Richard Ferrant CEA LETI MINATEC Grenoble France STMicroelectronics Private Limited Crolles France

The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques change the strength of individual cell transistor, thus modifying the cell stability during the first read access following a long period of idle mode. The conclusions of the paper show that letting the bit lines float during the idle mode is mandatory to diminish the cell leakage current and help to protect the cell content against the bit-line aggressions.

关键词： Random access memory Leakage current Microelectronics Voltage control IEEE members CMOS technology Protection Circuit stability Transistors Threshold voltage

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Committees

Committees

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

Provides a listing of current committee members.

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A generic method for variability analysis of nanoscale circuits

A generic method for variability analysis of nanoscale circu...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology Atlanta GA USA

We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric, and generic nature of the proposed method can greatly facilitate the technology-circuit co-design.

关键词： Circuit analysis Random access memory Circuit simulation Fluctuations Kernel Hardware Failure analysis SPICE Probability density function Circuit analysis computing

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TDDB and BTI reliabilities of high-k stacked gate dielectrics - Impact of initial traps in high-k layer -

TDDB and BTI reliabilities of high-k stacked gate dielectric...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Kenji Okada Hiroyuki Ota Toshihide Nabatame Akira Toriumi SCR Building MIRAI-ASET Tsukuba Ibaraki Japan AIST MIRAI-ASRC Japan University of Tokyo Japan

Reliabilities of high-k stacked gate dielectrics are discussed from the viewpoint of the impact of initial traps in high-k layer. TDDB reliability can be explained by the generated subordinate carrier injection (GSCI) model. While initial traps increase the leakage current, they do not degrade the TDDB reliability. In contrast, the BTI reliability is strongly degraded by initial traps.

关键词： High K dielectric materials High-K gate dielectrics Tunneling Degradation Breakdown voltage Electron traps Dielectric breakdown Charge carrier processes Materials reliability Electric breakdown

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Threshold voltage shift instability induced by plasma charging damage in MOSFETs with high-k dielectric

Threshold voltage shift instability induced by plasma chargi...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： K. Eriguchi M. Kamei K. Okada H. Ohta K. Ono Graduate School of Engineering Kyoto University Kyoto Japan MIRAI AIST Tsukuba Ibaraki Japan

Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO 2 ) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO 2 . For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer from negative charge trapping, whereas for Cl-plasma confirmed to induce less damage, both n- and p-ch MOSFETs with high-k gate stacks suffer from positive charge trapping, i.e., the direction of threshold voltage (V t ) shift depends on plasma sources and a amount of charging damage. From the results of constant-current stress tests, the present unique V t shifts were attributed to the characteristic hole and electron trapping phenomena, implying the necessity of taking the intrinsic charge trapping process into consideration for accurate evaluations of charging damage on high-k gate dielectrics.

关键词： Threshold voltage MOSFETs High-K gate dielectrics High K dielectric materials Plasma sources Plasma devices Electron traps Dielectric materials Dielectric measurements Capacitance-voltage characteristics

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Temperature-based phase change memory model for pulsing scheme assessment

Temperature-based phase change memory model for pulsing sche...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Yi-Bo Liao Jun-Tin Lin Meng-Hsueh Chiang Department of Electronic Engineering National I-Lan University Taiwan

A physical yet analytical phase change memory (PCM) model simultaneously accounting for thermal and electrical conductivities is presented. Due to the physics based nature of the model, the essential temperature from heating and cooling of PCM during operation is instantaneously updated. More importantly, the model can be applied to non-conventional circuit design technique. We show that for the first time the input current pulsing scheme for PCM programming can be significantly simplified via the unique intrinsic thermal memory effect. The model is implemented in HSPICE using Verilog-A, which is flexible and portable for different circuit simulators. As PCM technology is emerging, the predictive compact model can expedite the novel technology development.

关键词： Phase change memory Phase change materials Thermal conductivity Physics Temperature Heating Cooling Circuit synthesis Hardware design languages Flexible printed circuits

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Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS

Comparative analysis of two operational amplifier topologies...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Jose-Angel Diaz-Madrid Harald Neubauer Gines Domenech-Asensi Ramon Ruiz IC Design Department of the Fraunhofer Institute for Integrated Circuits Erlangen Germany Departamento de Electronica y Tecnologia de Computadoras Universidad Politecnica de Cartagena Cartagena Spain

This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for low power dissipation. All analog components of this pipeline ADC are fully differential, as there are dynamic comparators, analog multiplexers and operational amplifiers with gain boosting.

关键词： Operational amplifiers Topology Pipelines CMOS technology Analog-digital conversion Transient analysis Analytical models Power supplies Capacitors Power dissipation

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Statistical leakage modeling in CMOS logic gates considering process variations

Statistical leakage modeling in CMOS logic gates considering...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Carmelo D'Agostino Philippe Flatresse Edith Beigne Marc Belleville STMicroelectronics Crolles FTM/DAIS MINATEC CEA-LETI Grenoble CEA-LETI Grenoble MINATEC

The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical process variations. The developed methodology is completely based on BSIM4 equations, implemented in Verilog-A, and applicable to any different CMOS technologies (90 nm, 65 nm, etc), electrical simulators and models. For the first time subthreshold, gate, BTBT, and GIDL leakage variations are considered. Comparisons to Monte-Carlo simulation on 90 and 65 nm STMicroelectronics CMOS technologies fully validate the accuracy of the proposed method and demonstrate the efficiency of the proposed analysis method.

关键词： CMOS logic circuits Semiconductor device modeling CMOS process Logic gates CMOS technology Leakage current CMOS integrated circuits Gate leakage Differential equations Hardware design languages

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2008 IEEE International conference on Integrated Circuit Design and Technology

2008 IEEE International conference on Integrated Circuit Des...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

The following topics are dealt: advanced transistor structure, architecture and process; RF & AMS; low power electronics; reliability; system level technology assessment; DFM/DFT/DFY/DFR; advanced memory devices; ...

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Evaluation of Ultra Thin Body Si-On-ONO (UTB SOONO) transistors using ultra thin spacer technology

Evaluation of Ultra Thin Body Si-On-ONO (UTB SOONO) transist...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Hyun Jun Bae Sung Hwan Kim Sung In Hong Yong Lack Choi Ho Ju Song Chang Woo Oh Dong-Won Kim Donggun Park KyungSeok Oh Won-Seong Lee R&D Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea

Ultra Thin Body Si-On-ONO (UTB SOONO) transistors with ultra thin spacer are successfully demonstrated and evaluated. They have shown increased driving current more than 30% compared with conventional UTB SOONO transistors with thick spacer due to reduced source/drain resistance without short channel effect degradation by using thin spacer. In this paper, it is shown that thin spacer technology is very attractive to UTB SOI device in terms of device performance and process simplicity.

关键词： Space technology Immune system Silicon on insulator technology Fabrication Transistors CMOS process Silicon germanium Germanium silicon alloys Research and development Degradation

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