This paper presents the probabilistic logic model to compute the probability distribution of the nano gate states. The characterization is based on the markov random field and statistic physics. The primary logic gate...
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ISBN:
(纸本)9781424418107
This paper presents the probabilistic logic model to compute the probability distribution of the nano gate states. The characterization is based on the markov random field and statistic physics. The primary logic gates are probabilistically characterized. The effectiveness of the method is demonstrated by a full adder and an 8-bit adder. The analysis shows that the device probability distribution highly depends on the system structures and other performance parameters.
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mod...
详细信息
ISBN:
(纸本)9781424418107
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing a delay overlapping stage (DOS) chart. We propose a circuit design optimization and verification methodology that considers process variability.
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