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检索条件"丛书名=Theory in Practice"

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PVM parameter tuning to improve communication in distributed applications

PVM parameter tuning to improve communication in distributed...

引用

EUROMICRO Conference

作者： M. Giordano M.M. Furnari F. Vitobello CNR Istituto di Cibernetica Naples Italy

This paper presents experimental results of an investigation to efficiently exploit PVM communication on Network of Workstations (NoW) over ATM networks. Test results show that a better exploitation of ATM LAN bandwidth can be gained by tuning few parameters, both at PVM application program interface and PVM implementation level, such as PVM packet fragment size and TCP socket buffer size. Parameter tuning gave good communication performances compared with other PVM implementation that directly use the ATM Adaptation Layer instead of TCP/IP. It is foreseen that, on developing PVM distributed applications, better communication performances could be obtained through a careful network parameter setting.

关键词： Electrical capacitance tomography Libraries Concurrent computing Application software Workstations Local area networks TCPIP Standards development Writing ISO standards

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Automating SCM metric data collection and analysis in virtual software corporations

Automating SCM metric data collection and analysis in virtua...

引用

EUROMICRO Conference

作者： J. Ronkainen T. Rahikkala R. Blackwood Software Process Improvement Research Action Laboratory (SPIRAL) VTT Electronics and Infotech Oulu Oulu Finland British Aerospace (Defence Systems) Limited Glasgow UK

The Virtual Software Corporation (VSC) represents an organisational structure addressing the needs of distributed software development. Research indicates that Software Configuration Management (SCM) is one of the most important challenges faced by VSCs, requiring support and continued improvement. The real influences of the VSC structure on the SCM process are, however, not fully known yet. The aim of this paper is to present an approach to make the SCM process more visible within the VSCs.

关键词： Data analysis Aerospace electronics Organizational aspects Microwave integrated circuits Software measurement Electronic equipment testing Aerospace testing Laboratories Spirals Electronic switching systems

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Executable specification for multimedia supporting refinement and architecture exploration

Executable specification for multimedia supporting refinemen...

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EUROMICRO Conference

作者： C. Schneider Corporate Research Infineon Technologies Munich Germany

A VHDL-based methodology for top-down design, starting from an executable specification, supporting refinement towards RTL is proposed for the multimedia domain. The methodology is demonstrated using an MPEG-2 video decoder. A key idea for writing an initial executable specification is to keep the modeling style as close as possible to thinking in the domain. The executable specification is refined by partitioning the initially sequential model into concurrent processes and by moving functionality between blocks. During partitioning, control-dominated parts are separated from data-intensive calculations to enable domain-specific refinement. Finally the timing is refined from the causal to the clock-related level to enable performance simulation.

关键词： Data structures Decoding Electronic mail Clocks Timing Logic Space exploration Performance evaluation MPEG standards Java

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Technology driven multilevel logic synthesis based on functional decomposition into gates

Technology driven multilevel logic synthesis based on functi...

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EUROMICRO Conference

作者： R. Rzechowski L. Jozwiak T. Luba Institute of Telecommunications Warsaw University of Technology Warsaw Poland Section of Digital Information Systems EH 10.25 Eindhovan University of Technology Eindhoven Netherlands

In this paper a new method is proposed for multilevel logic synthesis based on functional decomposition into gates. Unlike the traditional approach to the decomposition, where the basic components of the decomposition network are the universal cells, we propose a method, which instead of cells uses gates, but preserves advantages of the functional decomposition. This approach makes possible to improve traditional FPGA functional decomposition onto the more general algorithm, which is also useful for other technologies in VLSI ASIC design.

关键词： Logic Network synthesis Field programmable gate arrays CMOS technology Modems Microelectronics Libraries Boolean functions Input variables Information systems

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Two-level logic synthesis on PAL-based CPLD and FPGA using decomposition

Two-level logic synthesis on PAL-based CPLD and FPGA using d...

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EUROMICRO Conference

作者： D. Kania Institute of Electronics Silesian Technical University Gliwice Poland

The PAL-based structure constitutes the kernel of many CPLD and FPGA devices. The problem of appropriate decomposition of the whole devices under design into suitable parts which can be realized as single PAL-based logic blocks containing the limited number of terms, is one of basic problems of the synthesis process. The method of two-level logic synthesis that makes use of three-state output buffers constituting the additional internal resources of logic blocks, is presented in this paper. Developed algorithms, implemented within the Decomp system, have been used for partitioning the benchmark circuits due to realization by means of the PAL-based logic blocks with the given number of terms. Synthesis of benchmark circuits for standard PAL20V8 devices has also been carried out and the obtained results have been compared to the ones published previously.

关键词： Logic Field programmable gate arrays Virtual reality Decision support systems

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Design space exploration in system level synthesis under memory constraints

Design space exploration in system level synthesis under mem...

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EUROMICRO Conference

作者： R. Szymanek K. Kuchcinski Department of Computer and Information Science Linköping University Sweden

This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constraints of different nature, such as cost, execution time, memory capacity and limitations on resource usage. Previous approaches have concentrated on a specific class of requirements and thus they limit number of constraints which can be handled in the design process. This results very often in non-feasible or too expensive solutions. The system presented in this paper CLASS (Constraint Logic bAsed System Synthesis) makes it possible to impose different design constraints and thus model the design more realistically. It is also efficient in finding good solutions or in some cases, optimal solutions for even nontrivial problems.

关键词： Space exploration Memory management Process design Distributed computing Embedded system Electronic switching systems Embedded computing Logic design Cost function Design methodology

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A dictionary-adaptive speech driven user interface for a distributed multimedia platform

A dictionary-adaptive speech driven user interface for a dis...

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EUROMICRO Conference

作者： J. Peltola J. Plomp T. Seppanen VTT Electronics Oulu Finland

The goal of the PRINCESS project is the development of a distributed end-to-end multimedia platform prototype. The platform supports access to media servers in a computer network via various types of mobile terminals. New paradigms for user interfaces are applied in order to make the terminal devices more intelligent and to enable hands-free operation for a busy user. A speech recognition module capable of recognising Finnish words has been integrated into the user interface. The vocabulary of command words is continuously restricted and adapted to the part of the user interface under control. The experimental system has been demonstrated in a distributed digital image retrieval application. Several different more conventional user interfaces may be used in the application, but the user may also opt to use a speech driven interface. Experiments show that the use of a dynamic vocabulary greatly reduces the recognition errors as compared to a fill set of command words in our application.

关键词： User interfaces Speech recognition Vocabulary Prototypes Network servers Computer networks Mobile computing Digital images Image retrieval Optimized production technology

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Index of authors

Index of authors

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EUROMICRO Conference

Presents an index of the authors whose papers are published in the conference.

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Application-dependent testing of FPGA delay faults

Application-dependent testing of FPGA delay faults

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EUROMICRO Conference

作者： A. Krasniewski Institute of Telecommunications Warsaw University of Technology Poland

To ensure correct operation of an FPGA based system with regard to timing characteristics, an application-dependent FPGA testing, i.e. testing of an FPGA programmed to implement a user-defined function, must be performed. We propose a procedure for application-dependent self testing of an in-circuit reprogrammable FPGA and develop BIST schemes that preserve the FPGA timing. For these schemes, the reconfiguration of a portion of the FPGA into test resources has no impact on the timing characteristics of that part of the FPGA which is currently being tested. We also present a method for enhancing the susceptibility of FPGA delay faults to random testing. It is based on modifying the functions of programmable logic components in the section under test. We compare the efficiency of the self-test scheme that uses this method with the earlier reported BIST techniques that rely on the design of test pattern generators best suited for pseudoexhaustive testing of delay faults.

关键词： Field programmable gate arrays Delay Timing Built-in self-test System testing Automatic testing Logic testing Performance evaluation Programmable logic arrays Programmable logic devices

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High level pre-synthesis optimization steps using hierarchical conditional dependency graphs

High level pre-synthesis optimization steps using hierarchic...

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EUROMICRO Conference

作者： A.A. Kountouris C. Wolinski Mitsubishi Electric ITE Rennes France

Taking advantage of existing High-Level Synthesis (HLS) tools is a possibility that merits consideration. Existing HLS technology took many years to develop and has reached a stage where complex combinations of optimization trade-off's can be handled. At this stage, developing a whole new tool chain based on a different internal representation seems to be quite impractical. Nevertheless it is always possible to add some high level optimizing step which permits to improve the performance of existing tools. In this context we propose high level pre-synthesis optimization using our HCDGs (Hierarchical Conditional Dependency Graph) as internal representation. Combination of pre-synthesis and powerful HCDG representation is a principal novelty of our approach. Experimental results using as target synthesis tool the SYNOPSYS behavioral compiler, show significant amelioration of the synthesis results.

关键词： High level synthesis Scheduling algorithm Hardware design languages Constraint optimization Signal synthesis Signal generators Tellurium Specification languages Time factors

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