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检索条件"丛书名=Tutorial"

共 546 条记录，以下是21-30 订阅

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Probabilistic modeling of nanoscale adder

Probabilistic modeling of nanoscale adder

引用

IEEE International Conference on Integrated Circuit Design and Technology

作者： Lu, Xiaojun Li, Jianping Yang, Guowu Song, Xiaoyu Univ Elect Sci & Technol Sch Comp Sci Chengdu Peoples R China Portland State Univ Dept ECE Portland OR 97207 USA

ISBN: (纸本)9781424418107

This paper presents the probabilistic logic model to compute the probability distribution of the nano gate states. The characterization is based on the markov random field and statistic physics. The primary logic gates are probabilistically characterized. The effectiveness of the method is demonstrated by a full adder and an 8-bit adder. The analysis shows that the device probability distribution highly depends on the system structures and other performance parameters.

关键词： digital circuit probability probability logic nanoelectronics

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The IEE tutorial Workshop on Arthing & Bonding Techniques for Electrical Installations - Cover

The IEE Tutorial Workshop on Arthing & Bonding Techniques fo...

引用

2006 The IEE tutorial Workshop on Earthing and Bonding Techniques for Electrical Installations (Ref. No. 2006/11305 and 2006/11306)

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Process variability-induced timing failures - A challenge in nanometer CMOS low-power design

引用

IEEE International Conference on Integrated Circuit Design and Technology

作者： Zhang, Xiaonan Bai, Xiaoliang Qualcomm Inc San Diego CA 92121 USA

ISBN: (纸本)9781424418107

This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing a delay overlapping stage (DOS) chart. We propose a circuit design optimization and verification methodology that considers process variability.

关键词： Timing CMOS process Delay CMOS technology Digital circuits Circuit synthesis Threshold voltage Robustness Inverters Semiconductor device modeling

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A low power 12-bit and 30-MS/s pipeline analog to digital converter in 0.35 μm CMOS

A low power 12-bit and 30-MS/s pipeline analog to digital co...

引用

IEEE International Conference on Integrated Circuit Design and Technology

作者： Fatah, Rarbi Daniel, Dzahini Univ Grenoble 1 INPG CNRS IN2P3 LPSC 53 Ave Martyrs F-38026 Grenoble France PSI Elect Co LPSC Lab New York NY USA

ISBN: (纸本)9781424418107

The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash. A CMOS 0.35 mu m process is used, and the dynamic range covered is 2V. The analog part of the converter can be quickly (a couple of mu s) switched to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The size of the converter's layout including the digital correction stage is only 1.7mm*0.6mm, and the total dc power dissipation is 35mW.

关键词： analog-digital conversion CMOS analog integrated circuits pipelined converter switched-capacitors

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Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/T...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： N. Collaert K. von Arnim R. Rooyackers T. Vandeweyer A. Mercha B. Parvais L. Witters A. Nackaerts E. Altamirano Sanchez M. Demand A. Hikavyy S. Demuynck K. Devriendt F. Bauer I. Ferain A. Veloso K. De Meyer S. Biesemans M. Jurczak IMEC Leuven Belgium Infineon Technologies Neubiberg Germany NXP-TSMC Research Center Heverlee Belgium K.U. Leuven ESAT-INSYS Heverlee Belgium

While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.

关键词： FinFETs Random access memory Tin Large scale integration Ring oscillators Scalability Implants Image motion analysis Optical devices Dielectrics

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A study of LBO effects in a 40 nm SA-MSCFET

A study of LBO effects in a 40 nm SA-MSCFET

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Jyi-Tsong Lin Yi-Chuen Eng Shiang-Shi Kang Department of Electrical Engineering National Sun Yat-Sen University Kaohsiung Taiwan

This work aims to examine and analyze carefully the effects of block oxide length (L BO ) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-aligned (SA) gate-to-body technique. In the MSCFET design the two key parameters are the length and the height of the block oxide which are so sensitive to the short-channel effects (SCEs). Because the research of the block oxide height (H BO ) has already been done as described in [1], in this study we will focus on the influence of L BO on the SA-MSCFET. Also, some preliminary characteristics of the new configuration developed are demonstrated by using TCAD simulations.

关键词： CMOS technology FETs Etching Insulation Silicon on insulator technology Numerical simulation Boron Epitaxial growth Substrates Sputtering

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An integrated class D audio amplifier based on sliding mode control

An integrated class D audio amplifier based on sliding mode ...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Gael Pillonnet Remy Cellier Nacer Abouchi Monique Chiollaz CPE Lyon INL Grenoble France

Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial circuit. Experimental IC results, using commercial 0.13 mum CMOS technology, verified the theoretical results: the efficiency is above 90%, THD is lower than 0.01% and PSRR is superior to 70 dB.

关键词： Sliding mode control Pulse width modulation Pulse amplifiers Power amplifiers CMOS technology Power generation Feedback Space vector pulse width modulation Frequency CMOS integrated circuits

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3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics

3D multichannels and stacked nanowires technologies for new ...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： T. Ernst E. Bernard C. Dupre A. Hubert S. Becu B. Guillaumot O. Rozeau O. Thomas P. Coronel J.-M. Hartmann C. Vizioz N. Vulliet O. Faynot T. Skotnicki S. Deleonibus CEA/LETI Grenoble France STMicroelectronics Private Limited Crolles France

Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I OFF (< 20 pA/mum) and high I ON (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.

关键词： Nanowires Nanoelectronics Tin Transistors FinFETs Silicon Etching Epitaxial growth Robustness CMOS technology

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Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -

Low-voltage limitations and challenges of nano-scale CMOS LS...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Kiyoo Itoh Central Research and Development Laboratory Hitachi Limited Kokubunji Tokyo Japan

The minimum operating voltage (V min ) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V min that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (V T ) of MOSFETs. The V min , however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce V T variations.

关键词： Random access memory Read-write memory Voltage Logic circuits CMOS logic circuits MOSFETs Degradation Subthreshold current Flip-flops Logic arrays

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CMOS SOI technology for WPAN. Application to 60 GHz LNA

CMOS SOI technology for WPAN. Application to 60 GHz LNA

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： A. Siligaris C. Mounet B. Reig P. Vincent A. Michel CEA LETI MINATEC Grenoble France Ansoft Corporation Buc France

This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip passive devices. A short description of the transistor model is also provided. Finally, we discuss the details of the LNA design and show how the simulation results compare to the measurements.

关键词： CMOS technology Electromagnetic waveguides Coplanar waveguides Analytical models Low-noise amplifiers CMOS process Microelectronics Semiconductor device modeling Electromagnetic modeling Electromagnetic scattering

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