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检索条件"丛书名=Tutorial"
546 条 记 录,以下是21-30 订阅
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Probabilistic modeling of nanoscale adder
Probabilistic modeling of nanoscale adder
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IEEE International Conference on Integrated Circuit Design and Technology
作者: Lu, Xiaojun Li, Jianping Yang, Guowu Song, Xiaoyu Univ Elect Sci & Technol Sch Comp Sci Chengdu Peoples R China Portland State Univ Dept ECE Portland OR 97207 USA
This paper presents the probabilistic logic model to compute the probability distribution of the nano gate states. The characterization is based on the markov random field and statistic physics. The primary logic gate... 详细信息
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The IEE tutorial Workshop on Arthing & Bonding Techniques for Electrical Installations - Cover
The IEE Tutorial Workshop on Arthing & Bonding Techniques fo...
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2006 The IEE tutorial Workshop on Earthing and Bonding Techniques for Electrical Installations (Ref. No. 2006/11305 and 2006/11306)
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Process variability-induced timing failures - A challenge in nanometer CMOS low-power design
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IEEE International Conference on Integrated Circuit Design and Technology
作者: Zhang, Xiaonan Bai, Xiaoliang Qualcomm Inc San Diego CA 92121 USA
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mod... 详细信息
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A low power 12-bit and 30-MS/s pipeline analog to digital converter in 0.35 μm CMOS
A low power 12-bit and 30-MS/s pipeline analog to digital co...
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IEEE International Conference on Integrated Circuit Design and Technology
作者: Fatah, Rarbi Daniel, Dzahini Univ Grenoble 1 INPG CNRS IN2P3 LPSC 53 Ave Martyrs F-38026 Grenoble France PSI Elect Co LPSC Lab New York NY USA
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an a... 详细信息
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Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length
Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/T...
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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
作者: N. Collaert K. von Arnim R. Rooyackers T. Vandeweyer A. Mercha B. Parvais L. Witters A. Nackaerts E. Altamirano Sanchez M. Demand A. Hikavyy S. Demuynck K. Devriendt F. Bauer I. Ferain A. Veloso K. De Meyer S. Biesemans M. Jurczak IMEC Leuven Belgium Infineon Technologies Neubiberg Germany NXP-TSMC Research Center Heverlee Belgium K.U. Leuven ESAT-INSYS Heverlee Belgium
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and... 详细信息
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A study of LBO effects in a 40 nm SA-MSCFET
A study of LBO effects in a 40 nm SA-MSCFET
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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
作者: Jyi-Tsong Lin Yi-Chuen Eng Shiang-Shi Kang Department of Electrical Engineering National Sun Yat-Sen University Kaohsiung Taiwan
This work aims to examine and analyze carefully the effects of block oxide length (L BO ) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-a... 详细信息
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An integrated class D audio amplifier based on sliding mode control
An integrated class D audio amplifier based on sliding mode ...
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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
作者: Gael Pillonnet Remy Cellier Nacer Abouchi Monique Chiollaz CPE Lyon INL Grenoble France
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This p... 详细信息
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3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics
3D multichannels and stacked nanowires technologies for new ...
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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
作者: T. Ernst E. Bernard C. Dupre A. Hubert S. Becu B. Guillaumot O. Rozeau O. Thomas P. Coronel J.-M. Hartmann C. Vizioz N. Vulliet O. Faynot T. Skotnicki S. Deleonibus CEA/LETI Grenoble France STMicroelectronics Private Limited Crolles France
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared... 详细信息
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Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -
Low-voltage limitations and challenges of nano-scale CMOS LS...
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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
作者: Kiyoo Itoh Central Research and Development Laboratory Hitachi Limited Kokubunji Tokyo Japan
The minimum operating voltage (V min ) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V min that is governed by SRAM cells rapidly increases as devices... 详细信息
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CMOS SOI technology for WPAN. Application to 60 GHz LNA
CMOS SOI technology for WPAN. Application to 60 GHz LNA
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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
作者: A. Siligaris C. Mounet B. Reig P. Vincent A. Michel CEA LETI MINATEC Grenoble France Ansoft Corporation Buc France
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Us... 详细信息
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