This paper presents the probabilistic logic model to compute the probability distribution of the nano gate states. The characterization is based on the markov random field and statistic physics. The primary logic gate...
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ISBN:
(纸本)9781424418107
This paper presents the probabilistic logic model to compute the probability distribution of the nano gate states. The characterization is based on the markov random field and statistic physics. The primary logic gates are probabilistically characterized. The effectiveness of the method is demonstrated by a full adder and an 8-bit adder. The analysis shows that the device probability distribution highly depends on the system structures and other performance parameters.
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mod...
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ISBN:
(纸本)9781424418107
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing a delay overlapping stage (DOS) chart. We propose a circuit design optimization and verification methodology that considers process variability.
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an a...
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ISBN:
(纸本)9781424418107
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash. A CMOS 0.35 mu m process is used, and the dynamic range covered is 2V. The analog part of the converter can be quickly (a couple of mu s) switched to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The size of the converter's layout including the digital correction stage is only 1.7mm*0.6mm, and the total dc power dissipation is 35mW.
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and...
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While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
This work aims to examine and analyze carefully the effects of block oxide length (L BO ) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-a...
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This work aims to examine and analyze carefully the effects of block oxide length (L BO ) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-aligned (SA) gate-to-body technique. In the MSCFET design the two key parameters are the length and the height of the block oxide which are so sensitive to the short-channel effects (SCEs). Because the research of the block oxide height (H BO ) has already been done as described in [1], in this study we will focus on the influence of L BO on the SA-MSCFET. Also, some preliminary characteristics of the new configuration developed are demonstrated by using TCAD simulations.
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This p...
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Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial circuit. Experimental IC results, using commercial 0.13 mum CMOS technology, verified the theoretical results: the efficiency is above 90%, THD is lower than 0.01% and PSRR is superior to 70 dB.
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared...
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Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I OFF (< 20 pA/mum) and high I ON (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.
The minimum operating voltage (V min ) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V min that is governed by SRAM cells rapidly increases as devices...
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The minimum operating voltage (V min ) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V min that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (V T ) of MOSFETs. The V min , however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce V T variations.
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Us...
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This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip passive devices. A short description of the transistor model is also provided. Finally, we discuss the details of the LNA design and show how the simulation results compare to the measurements.
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