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An innovative sub-32nm SRAM current sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

An innovative sub-32nm SRAM current sense amplifier in doubl...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Adam Makosiej Piotr Nasalski Bastien Giraud Andrei Vladimirescu Amara Amara DMCS Technical University of Lodz Lodz Poland Institut Superieur d'Electronique de Paris Paris France Berkeley Wireless Research Center Berkeley USA

This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease), less power consuming (313% power dissipation decrease) and much more resistant to transistor length (L) (125% gain) and threshold voltage mismatches (Vth) (233% gain).

关键词： Random access memory CMOS process MOS devices Capacitance Silicon on insulator technology Threshold voltage Predictive models Integrated circuit technology Monte Carlo methods Wireless sensor networks

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New state variable device opportunities for beyond CMOS: A system perspective

New state variable device opportunities for beyond CMOS: A s...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Victor V. Zhirnov Ralph K. Cavin George. I. Bourianoff Semiconductor Research Corporation Durham NC USA Intel Corporation Austin TX USA

As semiconductor technology moves closer to the ultimate physical limits for scaling of devices that utilize electrons as information bearing particles, many new opportunities for research in the physical sciences are emerging. If we look beyond the limits of scaling electron devices, many more challenging research opportunities exist in the areas of physics of information carriers and physics of communication. A trend, synergistic with scaling, is the use of semiconductor technologies for diverse integrated systems applications. Decreasing physical size of the system may increase both system capability and application space. Therefore, in parallel with device scaling trends and limits, in the second part of this talk we consider system scaling.

关键词： Switches Communication switching Physics Information processing Electron devices Space technology FETs Tunneling CMOS technology Throughput

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Ultra-high bandwidth memory with 3D-stacked emerging memory cells

Ultra-high bandwidth memory with 3D-stacked emerging memory ...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Keiko Abe Mihir P. Tendulkar John R. Jameson Peter B. Griffin Kumiko Nomura Shinobu Fujita Yoshio Nishi Advanced LSI Technology Laboratory Corporate R&D center Toshiba Corporation Kawasaki Japan Center for Integrated Systems University of Stanford CA USA Santa Clara University CA USA

To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO 2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential to achieve ultra-high bandwidth required for the future processors.

关键词： Bandwidth CMOS process Decoding USA Councils CMOS technology Driver circuits Large scale integration Frequency Through-silicon vias Switches

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A 0.5 V area-efficient transformer folded-cascode low-noise amplifier in 90 nm CMOS

A 0.5 V area-efficient transformer folded-cascode low-noise ...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Takao Kihara Hae-Ju Park Isao Takobe Fumiaki Yamashita Toshimasa Matsuoka Kenji Taniguchi Graduate School of Engineering Osaka University Osaka Japan

We present a low-voltage transformer folded- cascode CMOS low-noise amplifier (LNA). We reduce the chip area of the LNA by coupling an internal inductor and load inductor, and show the effects of the coupling on the LNA by using analytical expressions. The LNA, implemented with 90-nm digital CMOS technology, occupies 0.21 mm 2 and achieves S 11 < -10 dB, NF = 2.7 dB, and S 21 = 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW from a 0.5 V supply. The proposed LNA can replace the conventional folded-cascode LNA.

关键词： Low-noise amplifiers

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A simple compact model to analyze the impact of ballistic and quasi-ballistic transport on ring oscillator performance

A simple compact model to analyze the impact of ballistic an...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： S. Martinie G. Le Carval D. Munteanu M.-A. Jaud J.L. Autran UMR CNRS IMNP CNRS Marseilles France CEA-LETI Minatec Grenoble Grenoble France IMNP CNRSUMR CNRS Marseilles France Institut Universitaire Paris France

This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering processes through a dynamical mean free path. Using this model, CMOS inverters and ring oscillators have been simulated to highlight the impact of ballistic and quasi-ballistic transport on static and transient performance.

关键词： Performance analysis Ring oscillators Semiconductor device modeling Backscatter Analytical models Circuit simulation Scattering MOSFET circuits Physics Hardware design languages

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Reliability of advanced embedded non-volatile memories: The 2T-FNFN device

Reliability of advanced embedded non-volatile memories: The ...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Guoqiao Tao NXP Semiconductors Nijmegen Netherlands

The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can be determined by studying large flash arrays. Furthermore, the reliability challenges coming along with technology scaling are discussed.

关键词： Nonvolatile memory Character generation Tunneling CMOS technology Virtual private networks Logic programming Semiconductor device reliability Semiconductor devices Low voltage Logic devices

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3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM

3D CMOS integration: Introduction of dynamic coupling and ap...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： P. Batude M.-A. Jaud O. Thomas L. Clavelier A. Pouydebasque M. Vinet S. Deleonibus A. Amara CEA LETI MINATEC Grenoble France

This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (V TH ) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable V TH . This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology. Promising results in term of density and stability using TCAD simulations are shown for a 4T SRAM load-less cell.

关键词： Robustness Random access memory Stability Threshold voltage MOSFETs Dielectric substrates Temperature sensors Silicides CMOS technology Voltage control

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A new analytical model for predicting SWCNT band-gap from geometrical properties

A new analytical model for predicting SWCNT band-gap from ge...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Karim El Shabrawy Koushik Maharatna Darren M. Bagnall Bashir M. Al-Hashimi School of Electronics and Computer Science Southampton University Southampton UK

In the following paper we present a complete analytical model that predicts the band-gap (E g ) of single-walled carbon nanotubes (SWCNTs) directly from their diameter (d) and chiral angle (thetas). The proposed analytical model is based on two mathematical expressions that have been derived by curve-fitting the outcome generated from the third-nearest-neighbor tight-binding (TB) method in conjunction with the zone-folding technique. Tests performed on the model demonstrated that 82% of a set of both metallic and semiconducting CNTs were accurately distinguished. In addition, the maximum band-gap error recorded for the semiconducting tubes was 10%. The model was also verified against previously published experimental data where 17 out of 21 tubes were correctly predicted. Finally, it is shown that the proposed model computes E g with a speed that is 10 5 times faster compared to the third-nearest-neighbor TB method with zone-folding. The outcome of this work offers a fast and accurate technique for engineers who are seeking to simulate CNT based devices and want to ascertain the CNTpsilas electronic properties with respect to the geometrical variation manifested in their synthesis process.

关键词： Analytical models Photonic band gap Semiconductivity Carbon nanotubes Curve fitting Semiconductor device testing Performance evaluation Predictive models Computational modeling Solid modeling

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On-chip circuit for measuring jitter and skew with picosecond resolution

On-chip circuit for measuring jitter and skew with picosecon...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： K. A. Jenkins A.P. Jose Z. Xu K.L. Shepard IBM Thomas J. Watson Research Center Yorktown Heights NY USA Department of Electrical Engineering Columbia University New York NY USA

A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurements.

关键词： Circuits Clocks Latches Semiconductor device measurement Timing jitter Voltage Oscilloscopes Delay effects Phase measurement Time measurement

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Integration of SAW filters

Integration of SAW filters

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Tarak Hdiji Hassene Mnif Mourad Loulou Electronic and Information Technology Laboratory National Engineering School of Sfax L.E.T.I. Sfax Tunisia

Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important properties such as, high acoustic velocities, power durability and temperature stability. Simulation results are presented for different design of SAW filter and different piezoelectric substrates.

关键词： SAW filters Surface acoustic wave devices Micromachining CMOS technology Surface acoustic waves Acoustic waves CMOS integrated circuits Microwave integrated circuits Monolithic integrated circuits Fabrication

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