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Dynamic measurement of critical-path timing

Dynamic measurement of critical-path timing

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Alan J. Drake Robert M. Senger Harmander Singh Gary D. Carpenter Norman K. James IBM Research Austin TX USA IBM Research Yorktown Heights NY USA Advanced Micro Devices Inc. Austin TX USA IBM Systems Group Austin TX USA

A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive to 20 mV/bit A/C and 10 mV/bit DC voltage changes, and less than 10degC/bit temperature changes.

关键词： Timing Delay Monitoring Calibration Signal generators Control systems Voltage Temperature sensors Clocks Synchronization

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A futur view of SoC in the post 45nm era

A futur view of SoC in the post 45nm era

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Uming Ko TI USA

While the semiconductor industry has delivered tremendous advancements over the years, the 45nm process node era is still in its infancy with only ≪20% of the market actually utilizing this process node by 2010. There are still many, many more benefits to be realized from 45nm technology. Over the last two decades of semiconductor process technology advancements, the electronics industry has enjoyed continuous improvements in performance, reduction in power and reduction in die size. And, these trends are expected to continue into the future as the industry moves into 45nm and beyond. Dr. Uming Ko, Senior Fellow and Director of Wireless Chip Technology Center from Texas Instrument’s will talk about the future trends expected in the post 45nm era of process technology, continued improvements in performance, power and size. He will also assess the characteristics of different end products such as wireless handsets, advanced imaging and surveillance and medical electronics, to determine which semiconductor products and markets might be good candidates for driving advanced process nodes. Advanced process nodes beyond 45nm will continue to deliver the types of advancements we’ve experienced historically; however going forward there is an increasing need to assess which products make sense for advanced nodes regardless of what is technically feasible. Dr. Ko will evaluate SoC trends going forward and will discuss the broader, market-based considerations for technology decisions in the post 45nm era.

关键词： Microelectronics Circuits Research and development Research and development management Silicon Electronics industry Process design Pattern matching Energy consumption Error analysis

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Use of the p-floating shielding layer for improving electric field concentration of the recessed gate

Use of the p-floating shielding layer for improving electric...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Sang Jun Hwang Seung Woo Yu Jae In Lee Ey-Goo Kang Man Young Sung Department of Electrical Engineering Korea University Seongbuk-Gu South Korea Department of Information Technology Far East University Chungbuk South Korea

The recessed gate IGBT has a lower on-state voltage drop compared with the DMOS IGBT, because it doesn't have a JFET region. But due to the electric field concentration in the corner of the gate edge, the breakdow... 详细信息

关键词： Insulated gate bipolar transistors Breakdown voltage Implants Low voltage Fabrication Medical simulation Switches Immune system Information technology Electric variables

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Real-time neutron and alpha soft-error rate testing of CMOS 130nm SRAM: Altitude versus underground measurements

Real-time neutron and alpha soft-error rate testing of CMOS ...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： J.L. Autran P. Roche S. Sauze G. Gasiot D. Munteanu P. Loaiza M. Zampaolo J. Borel Institute of Materials Microelectronics and Nanosciences of Provence(IM2NPUMR CNRS 6242) University Institute of France Marseilles France STMicroelectronics Private Limited Crolles France Aix-Marseille University and CNRS Institute of Materials Microelectronics and Nanosciences of Provence (IM2NP UMR CNRS 6242) ASTEP Platform c/o Communauté des communes du Dévoluy F-05250 St Etienne en Dévoluy France Laboratoire Souterrain de Modane Modane France JB Research and Development Ferrière Saint Etienne en Devoluy France

This work reports real-time soft-error rate (SER) testing of semiconductor static memories in both altitude and underground environments to separate the component of the SER induced by the cosmic rays (i.e. primarily by atmospheric neutrons) from that caused by on-chip radioactive impurities (alpha-particle emitters). Two European dedicated sites were used to perform long-term real-time measurements with the same setup: the Altitude SEE Test European Platform (ASTEP) at the altitude of 2252 m and the underground laboratory of Modane (LSM, CEA-CNRS) under 1700 m of rock (4800 meters water equivalent). Experimental data obtained using 3.6 Gbit of SRAMs manufactured in CMOS 130 nm technology are reported and analyzed. Comparison with accelerated and simulated SER is also discussed.

关键词： Neutrons Random access memory Atmospheric measurements CMOS technology Semiconductor device testing Cosmic rays Semiconductor impurities Performance evaluation Laboratories Manufacturing

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Table of content

Table of content

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

Presents the table of contents for the proceedings of the 2008 IEEE International Conference on Integrated Circuit Design and Technology and tutorial.

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Design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique

Design of a current steering CMOS D/A converter with an adap...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Junho Moon Sanghoon Hwang Daeyoon Kim Heewon Kang Seungjin Yeo Doobock Lee Minkyu Song Semiconductor Science Department Dongguk University Seoul South Korea

While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control-switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8 V, 0.18 mum, 1-poly, 5-metal CMOS technology. It occupies 0.52 mm 2 of silicon area with 15.8 mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.

关键词： Switches Switching converters Adaptive control CMOS technology Semiconductor device modeling MOSFET circuits CMOS analog integrated circuits CMOS process Analog circuits Fabrication

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Design of ST planar integrated inductors based on INFINISCALE flow

Design of ST planar integrated inductors based on INFINISCAL...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： A. Noire S. Bergeon A. Olliver Y. Courant STMicroelectronics Private Limited France NFINISCALE Grenoble France

IC design is driven by two simultaneous trends: miniaturization of microelectronics technology, and telecommunication market expansion. When considered at a user level, these trends seem to be compatible: by making devices smaller, integration of a larger number of functionalities in your smart phone is made possible and thus boosts the development of the telecom market. From an IC designer point of view, both trends are challenging: On one side, the technology shrinkage, makes components/MEMS/circuits more and more sensitive to design/process parameter variations. This requires more than ever accurate predictions as early as possible in the design flow and better collaborations between designers and technologists. . On the other side, time-to-market diktat imposes short design cycles. Up to now, these constraints have been handled using iterative and time consuming techniques such as iterative try-and-error loops at design step and iterative loops between designers and technologists In order to overcome the IC design bottleneck InfiniScale [1] approach offers a proven solution by proceeding to a smart use of designers/technologists/physicists experiences. This solution based upon innovative and cost-effective behavioral modeling techniques, and a complete model-based flow generates designs optimized for performance in matters of hours. This paper presents the InfiniScale total solutions flow (modeling and sizing) applied to a ST microelectronics planar integrated inductor.

关键词： Inductors Iterative methods Microelectronics Smart phones Telecommunications Micromechanical devices Circuits Process design Collaboration Time to market

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Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell

Read and write circuit assist techniques for improving Vccmi...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Muhammad M. Khellah Ali Keshavarzi Dinesh Somasekhar Tanay Karnik Vivek De Circuits Research Lab Intel Corp Hillsboro OR USA

We review circuit techniques aimed at improving read and write stability of the smallest 6T SRAM cell typically used in microprocessorpsilas Last Level cache (LLC). We qualitatively compare three main approaches and g... 详细信息

关键词： Circuits Random access memory Decision support systems

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SOI chip design and charging damage

SOI chip design and charging damage

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Terence B. Hook IBM Microelectronics VT USA

In this paper we discuss some aspects of antennas in real designs in SOI technology, and show how the concepts manifest themselves in actual chips, where second-order effects such as resistance and the details of the processing sequence can play an important role. We also discuss the ramifications of a more recent technique which inserts bulk contacts into the SOI design, thereby imposing a bulk-like character to the antenna rules, while maintaining the performance advantages of SOI.

关键词： Chip scale packaging Antennas and propagation Electrons Microelectronics Insulation Isolation technology Circuit synthesis Integrated circuit interconnections Paper technology Circuit simulation

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Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects

Ring oscillator circuit structures for measurement of isolat...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Jae-Joon Kim Rahul Rao Saibal Mukhopadhyay Ching-Te Chuang IBM Thomas J. Watson Research Center Yorktown Heights NY USA Georgia Institute of Technology Atlanta GA USA National Chiao Tung University Hsinchu Taiwan

Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI and the PBTI effects separately while conserving the simplicity and efficiency of a ring oscillator based circuit. We also show that the proposed circuits have better sensitivity to the NBTI effect than conventional ring-oscillator circuit when they are used in technologies that experience negligible PBTI effect.

关键词： Ring oscillators Niobium compounds Titanium compounds Degradation CMOS technology Circuit optimization Negative bias temperature instability MOS devices High-K gate dielectrics Isolation technology

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