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Virtual design for technology exploration - a process design integration methodology for a fabless entity -

Virtual design for technology exploration - a process design...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Christopher Chun Jose Corleto Matt Nowak Riko Radojcic Qualcomm Cdma Technologies San Diego CA USA

The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to allow co-optimization all the way up to the architecture level, is proposed. A virtual design flow of a potential product that allows rapid estimation of performance, power and cost attributes, as a function of a given set of process or design assumptions is proposed. Key features of such a virtual flow, and a summary of the attributes of several candidate point tools is presented. The accuracy requirements of the dasiapredictivepsila models required to enable this flow are assessed and discussed. A few example applications of the proposed methodology are presented to illustrate the use model, to define the required attributes of the virtual design flow, and to contrast this concept versus use of spreadsheets on one hand, or use of traditional design flows on the other.

关键词： Process design Phase change random access memory Cost function Predictive models Design methodology Prediction methods System analysis and design Technology forecasting Packaging FinFETs

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3D Contactless communication for IC design

3D Contactless communication for IC design

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Roberto Canegallo Luca Ciccarelli Federico Natali Alberto Fazzi Roberto Guerrieri PierLuigi Rolandi STMicroelectronics Private Limited Agrate-Brianza Italy ARCES University of Bologna Italy

3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme with transmitter and receiver circuits implemented in 0.13mum CMOS technology and connected to 8x8mum 2 electrodes in the upper metal layer of different dies and with face-to-face assembly, makes available a throughput of more than 22Mbps/mum 2 with 80muW/Gbps energy consumption.

关键词： Integrated circuit interconnections Power system interconnection CMOS technology High speed integrated circuits Signal design Coupling circuits Stress Wire Bonding Transmitters

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Device architectures based on graphene channels

Device architectures based on graphene channels

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： M. Baus T.J. Echtermeyer B.N. Szafranek M.C. Lemme H. Kurz Applied Micro and Optoelectronic GmbH Aachen Germany

Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for f... 详细信息

关键词： Silicon Carbon nanotubes MOSFET circuits CMOS technology Optical saturation Dielectric substrates Voltage FETs Transistors Semiconductor materials

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Technology development driven by design

Technology development driven by design

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Axel Nackaerts NXP Semiconductors Belgium Leuven Belgium

This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.

关键词： Libraries Timing Delay Circuit synthesis Design optimization Space technology Paper technology Logic devices Logic circuits Threshold voltage

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Plenary & workshop sessions

Plenary & workshop sessions

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

Provides a schedule of conference events and a listing of which papers were presented in each workshop.

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Stochastic analysis for crosstalk noise of coupled interconnects with process variations

Stochastic analysis for crosstalk noise of coupled interconn...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Xin Li Janet M. Wang Weiqing Tang Huizhong Wu Nanjing University of Science and Technology of PLA Nanjing China University of Arizona Tucson AZ USA Institute of Computing Technology Chinese Academy of Sciences Beijing China

This paper proposes a new approach to analyze crosstalk of coupled interconnects in the presence of process variations. The suggested method translates correlated process variations into orthogonal random variables by principle component analysis (PCA). combined with polynomial chaos expression (PCE), the technique utilizes Stochastic Collocation Method (SCM) to analyze the system response of coupled interconnects. A finite representation of interconnect crosstalk is obtained by projecting the infinite series representation onto a finite dimensional subspace. Experimental results demonstrate that the approach match well with HSPICE. The differences between the crosstalk obtained from the analytical method and HSPICE is about 2% or less. Furthermore the new approach shows good computation efficiency: much less running time has been observed over Monte Carlo SPICE simulation.

关键词： Stochastic resonance Crosstalk Random variables Principal component analysis Polynomials Chaos Stochastic systems Monte Carlo methods SPICE Computational modeling

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New writing mechanism for reliable SONOS embedded memories with thick tunnel oxide

New writing mechanism for reliable SONOS embedded memories w...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Michiel van Duuren Nader Akil Mohamed Boutchich Dusan S. Golubovic NXP-TSMC Research Center Leuven Belgium

This paper describes a new low-cost non-volatile embedded memory option for sub-100 nm CMOS processes, based on the SONOS (silicon-oxide-nitride-oxide-silicon) concept. The retention issue inherent to SONOS memories was solved by increasing the thickness of the tunnel oxide from 2 nm to 4-6 nm which is sufficient for operation temperatures up to 100degC. Because of the thicker tunnel oxide, the conventional way of erasing SONOS memory cells by means of hole tunneling can not be used anymore; therefore, a new writing mechanism, punch-through assisted hot hole injection, was developed. This mechanism has a high write speed (~100 mus) at moderate voltages (absolute biases are below 5-6 V). Thanks to these low operation voltages, no dedicated high-voltage transistors are needed, thus reducing the integration costs of the memory significantly.

关键词： Writing SONOS devices Quadratic programming Virtual reality Fiber reinforced plastics Decision support systems

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Synergy between design and process: A key factor in the evolving microelectronic landscape

Synergy between design and process: A key factor in the evol...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Michel Brillouet CEA-LETI France

In scaling down the dimensions of the transistors in integrated circuits, major issues need to be solved. As we approach the resolution limit of the lithographic tool, extensive modifications of the patterns need to be performed on the mask in order to match the expected features on the circuit. More and more trade-offs need to be addressed in designing complex circuits like power consumption, variability, error rate, etc.: a better interplay between the technology constraints and the design complexity has to be developed. Moving to non conventional CMOS (e.g. FinFET) induces specific issues to be dealt with through the design style. On the far end of this spectrum emerging research devices and architectures, as they are called in the ITRS roadmap, may need ‘out-of-the box’ thinking in the way complex systems and applications will be integrated.

关键词： Process design Microelectronics CMOS technology Research and development Circuits Research and development management Silicon Telecommunications CMOS process Electronics industry

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Building a reliable internet core using soft error prone electronics

Building a reliable internet core using soft error prone ele...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Allan L. Silburt Adrian Evans Ana Burghelea Shi-Jie Wen David Ward Ron Norrish Dean Hogle

This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design process. The system can then be modeled at an early stage to support design decisions and trade-offs related to potentially costly mitigation strategies. The design loop is closed with an accelerated measurement technique using neutron beam irradiation to confirm that the final product meets the specification.

关键词： Internet Single event upset Buildings Electronic components Computer architecture Silicon Software design Acceleration Measurement techniques Particle beams

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SONOS memories with embedded silicon nanocrystals in nitride by in-situ deposition method

SONOS memories with embedded silicon nanocrystals in nitride...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Yi-HongWu Tsung-Yu Chiang Sheng-Hsien Liu Wen-Luh Yang Tien-Sheng Chao Fun-Tat Chin Department of Electronic Engineering Feng Chia University Taichung Taiwan Department of Electrophysics National Chiao Tung University Hsinchu Taiwan

In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by in-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si 3 N 4 storage layer by dissociation of dichlorosilane (SiH 2 Cl 2 ) gas to a high density of 9 times 10 11 cm -2 . This new structure exhibits larger memory windows for up to 6 V, better program/erase characteristics, and excellent data retention properties as compared to control device. In addition, this novel process is simple, low cost, and compatible to the standard complementary metal-oxide-semiconductor (CMOS) processes. This technology seems to be very promising for the advanced flash memory devices.

关键词： SONOS devices Silicon Nanocrystals Fabrication Nonvolatile memory Chemical processes Size control Costs CMOS technology Threshold voltage

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