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A low power multi-band selector DLL with wide-locking range

A low power multi-band selector DLL with wide-locking range

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Ko-Chi Kuo Yi-Hsi Hsu Department of Computer Science and Engineering National Sun Yat-sen University Kaohsiung Taiwan

A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The operation frequency can be ranged from 250 MHz to 900 MHz. The static phase error is 6.75 ps and 23.65 ps at 250 MHz and 900 MHz respectively. The power dissipation is 14.5 mW at 900 MHz. The circuit is designed by using TSMC 0.18- mu m single-poly six-metal CMOS process.

关键词： Circuits Phase frequency detector Switches Voltage control Delay lines Charge pumps Phase locked loops Voltage-controlled oscillators Clocks Jitter

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Analysing the effect of process variation to reduce parametric yield loss

Analysing the effect of process variation to reduce parametr...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： H. Ramakrishnan S. Shedabale G. Russell A. Yakovlev School of Electrical Electronic and Computer Engineering University of Newcastle UK

For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently it is no longer feasible to optimise the process during the product lifetime resulting in an increase in parametric yield loss. This paper describes the use a combination of two statistical tools namely Design of Experiments (DoE) and Response Surface Modelling (RSM) which permit the identification and modelling of those process parameters whose variation which will impact most on the performance of a circuit. The efficiency of this approach, compared to using a Monte Carlo analysis, is demonstrated with respect to a Mutual Exclusion Element (MUTEX) which is used extensively in synchronisers where process variations can have considerable impact on circuit performance. To obtain the same modelling accuracy, the Monte Carlo approach would require large number of simulations compared to nine using the DoE scheme with the low computational overhead. This method can be used by semiconductor manufacturers and design house alike to bridge the gap between manufacture and design.

关键词： Semiconductor device manufacture Manufacturing processes Monte Carlo methods Semiconductor process modeling Foundries Response surface methodology Performance analysis Circuit optimization Microprocessors Statistical analysis

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A comparative study of variability impact on static flip-flop timing characteristics

A comparative study of variability impact on static flip-flo...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： B. Rebaud M. Belleville C. Bernard M. Robert P. Maurine N. Azemard CEA-LETI Minatec Grenoble France LIRMM CNRS Universite Montpellier II Montpellier France

With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article aims at comparing a set of representative static flip-flop architectures used in digital designs and at studying their sensitivity to process variations. Clock-to-Q delay, hold time and setup time means and standard deviations are compared for a low power 65 nm technology and commented. Then, a study of the hold/setup time failure probabilities according to the flip-flop used in a critical path is given to illustrate their robustness toward process variations.

关键词： Flip-flops Timing Clocks Latches Master-slave Circuits Delay effects Robustness Inverters Probability

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Independent-gate four-terminal FinFET SRAM for drastic leakage current reduction

Independent-gate four-terminal FinFET SRAM for drastic leaka...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Kazuhiko Endo Shin-ichi O'uchi Yuki Ishikawa Yongxun Liu Takashi Matsukawa Kunihiro Sakamoto Meishoku Masahara Junichi Tsukada Kenichi Ishii Hiromi Yamauchi Eiichi Suzuki Nanoelectronics Research Institute National Institute for Advanced Industrial Science and Technology Tsukuba Ibaraki Japan

An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible V th controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the V th of the 4T-FinFET, we have successfully demonstrated the reduction of the leakage current and power consumption of the SRAM cell.

关键词： FinFETs Random access memory Leakage current Etching Circuits Energy consumption Tin Resists Fabrication Acceleration

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Transconductance enhancement of Si nanowire transistors by oxide-induced strain

Transconductance enhancement of Si nanowire transistors by o...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： A. Seike T. Tange I. Sano Y. Sugiura I. Tsuchida H. Ohta T. Watanabe D. Kosemura A. Ogura I. Ohdomari T. Tomoyuki Waseda Daigaku Shinjuku-ku Tokyo JP Faculty of Science and Engineering Waseda University Shinjuku Tokyo Japan Meiji University School of Science and Technology Kanagawa Japan Institute for Nanoscience and Nanotechnology Shinjuku Tokyo Japan

Transconductance (g m ) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of g m are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation reveal predominantly horizontal tensile stress in the nwFET channels. The Raman spectra features in the strain controlled devices display an increase in the full width half maximum, and a shift to lower wavenumber confirming that g m enhancement is due to tensile stress introduced by the PADOX approach.

关键词： Transconductance Capacitive sensors Strain control MOSFET circuits Nanoscale devices CMOS technology Tensile strain Physics Displays FETs

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New charge trapping phenomena in Recessed-Channel-Array-Transistor (RCAT) after Fowler-Nordheim stress

New charge trapping phenomena in Recessed-Channel-Array-Tran...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Sung-Young Lee Se Geun Park Samjin Hwang Jaeeun Jeon Wonshik Lee DRAM QA Samsung Electronics Company Limited Hwasung Kyunggi South Korea

We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically changed. We have summarized the electrical characteristics of RCAT fabricated with different gate stack processes.

关键词： Random access memory Electron traps Oxidation Silicon compounds Wet etching Neck Thermal stresses Writing Electric variables DRAM chips

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A new edge termination technique to improve voltage blocking capability and reliability of field limiting ring for power devices

A new edge termination technique to improve voltage blocking...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Yo Han Kim Han Sin Lee Sin Su Kyung Young Mok Kim Ey Goo Kang Man Young Sung Department of Electrical Engineering Korea University Seoul South Korea Department of Information Technology Far East University South Korea

A planar edge termination technique of trenched field limiting ring is investigated by using 2-dimensional numerical analysis and simulation. The better voltage blocking capability and reliability can be obtained by trenching the field-limiting ring site which would be implanted. The trench etch step makes the junction depth deeper so that junction curvature effect and surface breakdown are less happened. The numerical analyses reveal two facts that the trenched field limiting ring has smaller maximum electric field and the electric field peak is deeper from the substrate surface, hence silicon dioxide layer can be protected. Therefore the voltage blocking capability and reliability of the new structure can be improved. The simulated results for 1700 V power devices by using TMA MEDICI show that the trenched field limiting ring can have smaller critical electric field and accomplish near 30% increase of breakdown voltage in comparison with the conventional structure. The proposed structure is more efficient to support voltage and more easy to gain the optimized design. Moreover, the fabrication of trenched field-limiting ring is relatively simple because the trench etch step uses the same mask of p+ field-ring implantation step. Extensive device simulations as well as qualitative analyses confirm these conclusions.

关键词： Voltage Numerical analysis Analytical models Etching Numerical simulation Electric breakdown Silicon compounds Protection Medical simulation Design optimization

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A 3-tier, 3-D FD-SOI SRAM macro

A 3-tier, 3-D FD-SOI SRAM macro

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Aamir Zia Philip Jacob Russell P. Kraft John F. McDonald Center for Integrated Electronics Rensselaer Polytechnic Institute Troy NY USA

Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although the reduction is not enough to have a significant effect on access time of the memory. It is argued that the major performance benefit obtained by 3D integration is in term of very wide data bus that can be realized much more easily with 3D structures as compared to 2D memories.

关键词： Random access memory Integrated circuit interconnections Decoding Wafer bonding Etching Delay effects CMOS technology Reduced instruction set computing Three-dimensional integrated circuits Clocks

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The future of flash memory: Is floating gate technology doomed to lose the race?

The future of flash memory: Is floating gate technology doom...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Dirk Wellekens Jan Van Houdt

Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials to extend floating gate scaling and explores the possibilities and promises these materials offer to further extend the floating gate concept as the dominant flash technology.

关键词： Flash memory Nonvolatile memory High K dielectric materials High-K gate dielectrics Aluminum oxide Character generation Silicon on insulator technology Dielectric losses Voltage Semiconductor materials

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2008 IEEE International conference on Integrated Circuit Design and Technology

2008 IEEE International conference on Integrated Circuit Des...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

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