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Low power clocking strategies in deep submicron technologies

Low power clocking strategies in deep submicron technologies

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： M. Samy Hosny Yuejian Wu Silicon Pro Ottawa ONT Canada Nortel Networks Limited Ottawa ONT Canada

Recent silicon process technology advancements have given chip designers integration capabilities never were possible before, and have led to a new wave of complex ASICs (applied specific integrated circuits). These advanced processes come with new challenges. This paper presents some of the challenges in deep submicron technologies, which require new design practices. We demonstrate some issues related to clocking strategies and timing closure that were encountered during the design of a FEC40 ASIC, and a methodology is proposed to mitigate some of these issues. The FEC40 ASIC is a forward error correction chip designed for Nortelpsilas 40 Gb/s coherent optical transmission system. The chip has about 11 million gates at a core frequency of 350 MHz and has 70 clock domains. The chip was fabricated in a 90 nm technology.

关键词： Clocks Timing Integrated circuit interconnections Integrated circuit technology Application specific integrated circuits Voltage Temperature Delay effects Manufacturing processes Process design

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A Localized Power Control mixing hopping and Super Cut-Off techniques within a GALS NoC

A Localized Power Control mixing hopping and Super Cut-Off t...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： E. Beigne F. Clermidy S. Miermont Y. Thonnart A. Valentian P. Vivet MINATEC CEA LETI Grenoble France

In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. We propose in this paper a complete dynamic voltage and frequency scaling architecture for IP units within a GALS NOC. network-on-chip architecture combined with a globally asynchronous locally synchronous paradigm is a natural enabler for DVFS mechanisms. GALS NoC provides scalable communications and a natural split between timing domains. The proposed low power architecture is based on the association of a local clock generator and a local power control mixing VDD-hopping and super cut-off techniques. No fine control software is required during voltage and frequency scaling. A minimal latency cost is observed together with an efficient local power control.

关键词： Power control Network-on-a-chip Frequency Dynamic voltage scaling Timing Computer architecture Clocks Power generation Voltage control Communication system control

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Sleep circuit for SRAM core with improved noise-margin

Sleep circuit for SRAM core with improved noise-margin

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Piyush Jain Jitendra Dasani Ashish Kumar STMicroelectronics Private Limited Greater Noida India

Data retention power gating is a commonly used method for leakage reduction in deep submicron SRAM. However, application of such methods result into reduced stability of the SRAM bitcell. Moreover, reducing supply voltage and increasing process variation put a limitation on such usage in deep submicron processes. Present scheme describes a method to enhance stability while applying such data retention power gating to SRAM memory core. Method improves stability under cross-corner/high-leakage conditions using a feedback mechanism. Minimum functional voltage under data retention power gating is reduced up to 11% of VDD using the described scheme, while using 90 nm CMOS process. The scheme enables the memory usage under low voltage operation, where we observe data retention failures using normal gating methods.

关键词： Sleep Random access memory Circuit noise Stability Low voltage Feedback Light emitting diodes Leakage current Noise reduction MOS devices

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Key considerations given to the design of a next generation multi-core communications platform

Key considerations given to the design of a next generation ...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Dac C. Pham Freescale Semiconductor Inc. Austin TX USA

Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power. However, this ever increasing application performance requirement can no longer be sustained without leveraging multi-core and on-demand acceleration. The paper presents the design considerations for the next generation multi-core communications platform.

关键词： Acceleration Fabrics Frequency Process control Bandwidth Yarn Pipelines System performance Costs Communication system control

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Overview of DFT features of the Sun Microsystems Niagara2 CMP/CMT SPARC chip

Overview of DFT features of the Sun Microsystems Niagara2 CM...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Tom Ziaja Murali Gala Sun Microsystems Inc.

The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed defects. In addition, this paper addresses issues involved in SOC testing in the absence of IEEE 1500.

关键词： Sun Logic testing Logic arrays Design for testability Logic design Automatic test pattern generation Built-in self-test Libraries Manufacturing Ethernet networks

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Proceedings 2008 IEEE International conference on Integrated Circuit Design and Technology [Front matter]

Proceedings 2008 IEEE International conference on Integrated...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original conference proceedings.

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Author index

Author index

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

The author index contains an entry for each author and coauthor included in the proceedings record.

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Analysis of Si substrate damage induced by inductively coupled plasma reactor with various superposed bias frequencies

Analysis of Si substrate damage induced by inductively coupl...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Y. Nakakubo A. Matsuda M. Kamei H. Ohta K. Eriguchi K. Ono Graduate School of Engineering Kyoto University Kyoto Japan

Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry (SE), photoreflectance spectroscopy (PR) and capacitance-voltage (C-V) measurement. The SE identified the interfacial layer growth by an optimized optical model, and the PR, the structural strain change and carrier trap site generation in IL, in accordance with a bias power and a superposed bias configuration. The aerial trap site density was estimated on the basis of a PR-based model. Also C-V measurement confirmed the surface and interfacial layer growth and carrier trap site generation in the vicinity of plasma-exposed surface. The obtained findings imply that superposed bias configurations, widely believed inevitable for future plasma processing, should be optimized in terms of Si substrate damage quantitatively estimated by the methods presented in this article.

关键词： Inductors Frequency Plasma measurements Plasma sources Capacitance-voltage characteristics Spectroscopy Plasma density Plasma materials processing Ellipsometry Capacitance measurement

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A novel moment-based methodology for accurate and efficient static timing analysis

A novel moment-based methodology for accurate and efficient ...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Ahmed Shebaita Dusan Petranovic Yehea Ismail EECS Department Northwestern University Evanston IL USA Mentor Graphics Wilsonville OR USA

A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the load is very accurate. A gate and input capacitance characterization is proposed which provides for accuracy, efficiency and flexibility in the path performance calculation. To illustrate the concept and prove its merits, multiple examples are presented. The method is an order to two orders of magnitude faster than current source based one, while it maintains accuracy within 5% of SPICE.

关键词： Timing Integrated circuit interconnections Frequency domain analysis Capacitance Performance analysis Propagation delay SPICE Circuit simulation Electronic design automation and methodology Predictive models

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Metal gate effects on a 32 nm metal gate resistor

Metal gate effects on a 32 nm metal gate resistor

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Thuy Dao Ik_Sung Lim Larry Connell Dina H. Triyoso Youngbog Park Charlie Mackenzie Freescale Semiconductor Inc. Austin TX USA Freescale Semiconductor Inc. Tempe AZ USA Freescale Semiconductor Inc. Lake Zurich IL USA

CMOS technology scaling has allowed for unprecedented integration of analog and digital circuits onto a single chip. The integration of RF and analog circuits with digital logic has provided the consumer with wireless devices with high performance and increasing functionality but at lower cost. System-on-chip (SOC) is considered the ultimate goal for a low cost, high performance semiconductor chip for mobile products. At the 32 nm node, high-K and metal gate will be the mainstream gate stack in high volume manufacturing. In this paper, we will review SOC requirements with a focus on high-K / metal gate effects on analog passive devices. We will present a new metal gate resistor which can be programmed to exhibit either a positive , negative, or zero temperature coefficient (TC) by adjusting its physical dimensions. We will also discuss the trade-offs that RF / analog designers will have to take into consideration.

关键词： Resistors CMOS technology Radio frequency High K dielectric materials High-K gate dielectrics CMOS digital integrated circuits CMOS analog integrated circuits Digital circuits Analog circuits CMOS logic circuits

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