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An SOI-based self-aligned quasi-SOI MOSFET with π-shaped semiconductor conductive layer

An SOI-based self-aligned quasi-SOI MOSFET with π-shaped se...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Yi-Chuen Eng Jyi-Tsong Lin Shiang-Shi Kang Department of Electrical Engineering National Sun Yat-sen University Kaohsiung Taiwan

A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D) tie and a block oxide island (BOI) under the channel, the SA-piFET, by minimizing the self-heating and charge sharing issues, thus manages to obtain better stability and reliability. Based on two-dimensional (2-D) simulations, the S/D tie serves to reduce the lattice-atom thermal vibrations and the BOI under the channel is used to control the short-channel effects (SCEs). Also, although the electrical characteristics of the SA-piFET are somewhat worse than the SA recessed S/D (ReS/D) ultra-thin (UT) SOI, it works without self-heating increasing.

关键词： MOSFET circuits FETs Silicon on insulator technology Electric variables Thermal stability MOS devices Semiconductor films Insulation Thermal resistance Semiconductor device reliability

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Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

Energy-efficient and metastability-immune timing-error detec...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Keith A. Bowman James W. Tschanz Nam Sung Kim Janice C. Lee Chris B. Wilkerson Shih-Lien L. Lu Tanay Karnik Vivek K. De Intel Corporation Hillsboro OR USA

Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (V CC ) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal V CC or at least 17% VCC reduction at equal throughput, resulting in 31 to 37% total power reduction.

关键词： Energy efficiency Metastasis Clocks Throughput Circuit testing Frequency Voltage Temperature distribution Error correction Silicon

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Reliability issues for nano-scale CMOS dielectrics: - From transistors to product reliability - - From SiON to high-k dielectrics -

Reliability issues for nano-scale CMOS dielectrics: - From t...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： G. Ribes M. Rafik D. Roy J.M. Roux STMicroelectronics Private Limited Crolles France

Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues, new materials as metal gates and high-k gate dielectrics have been integrated. These new materials require that we gain understanding of the reliability physics related to these new materials and that we develop high confidence-level design rules. These new materials require a high understanding level of their reliability issues, as well as the development of high confidence level design rules.

关键词： High-K gate dielectrics High K dielectric materials Materials reliability Dielectric materials Integrated circuit reliability Costs Reliability engineering Current density Voltage Inorganic materials

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How does inversed temperature dependence affect timing sign-off

How does inversed temperature dependence affect timing sign-...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Sean H. Wu Alexander Tetelbaum Li-C. Wang University of California Santa Barbara USA Lsi Corporation USA

As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may decrease as temperature increases. ITD posts a new challenge for timing sign-off because the highest and lowest sign-off temperatures may no longer be the worst-case and best-case timing corners. This work discuss the effect of ITD and its implication on timing sign-off, based on a standard cell library used in a typical design flow.

关键词： Temperature dependence Timing Temperature sensors Libraries Low voltage Large scale integration Delay effects Circuits Propagation delay Electron mobility

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Energy delay optimization methodology for current-mode signaling for on-chip interconnects

Energy delay optimization methodology for current-mode signa...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Astria Nur Irfansyah Torsten Lehmann Saeid Nooshabadi School of Electrical Engineering and Telecommunications University of New South Wales Sydney Australia Department of Information and Communications Gwangju Institute of Science and Technology Gwangju South Korea

Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend on each other. The methodology will be validated using the SPICE simulations. It will be shown that when dealing with the receiver termination sizing, the optimal size is determined by the voltage swing required by the noise margin.

关键词： Delay Optimization methods Driver circuits Integrated circuit interconnections Voltage Power dissipation Wire Impedance Energy dissipation Circuit simulation

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Traces of errors due to single ion in floating gate memories

Traces of errors due to single ion in floating gate memories

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： G. Cellere A. Paccagnella A. Visconti M. Bonanomi R. Harboe-Sorensen A. Virtanen Dipartimento di Ingegneria dellInformazione Universita di Padova Italy STMicroelectronics FTM Advanced R and D Agrate-Brianza Italy ESTEC European Space Agency Noordwijk Netherlands Department of Physics University of Jyvaskyla Finland

Single, high energy, high LET, ions impacting on a Floating gate array at grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Every time a FG is crossed by a single ion, it experiences a charge loss which permanently degrades the stored information. If the ion crosses more than one FG, the threshold voltage of all those FGs interested by its track will be degraded.

关键词： Nonvolatile memory Degradation Single event upset Error correction Ion beams Threshold voltage Random access memory Space technology Circuits Research and development

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3D-structured on-chip buck converter for distributed power supply system in SiPs

3D-structured on-chip buck converter for distributed power s...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Makoto Takamiya Kohei Onizuka Takayasu Sakurai Institute of Industrial Science University of Tokyo Tokyo Japan

An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency dependence on the filter inductor are also discussed.

关键词： System-on-a-chip Buck converters Power supplies Filters Stacking Manufacturing Switching converters Switching frequency Glass Inductors

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Design of a 6-bit 1GSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications

Design of a 6-bit 1GSPS fully folded CMOS A/D converter for ...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Doobock Lee Seungjin Yeo Heewon Kang Daeyoon Kim Junho Moon Minkyu Song Semiconductor Science Department Dongguk University Seoul South Korea

In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of 1 GHz, the ADC achieves an effective resolution bandwidth (ERBW) of 200 MHz, while consuming only 60 mW of power. The measured INL and DNL are within plusmn0.7LSB, plusmn0.5LSB, respectively. The measured SNDR is 33.64 dB, when Fin=100 MHz at Fs=1 GHz. The active chip occupies an area of 0.27 mm2 in 0.18 mum CMOS technology.

关键词： Ultra wideband technology Preamplifiers Feedback amplifiers Interpolation Linearity Energy consumption Analog-digital conversion Bandwidth Semiconductor device measurement CMOS technology

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Silicon-On-Nothing (SON) applications for Low Power technologies

Silicon-On-Nothing (SON) applications for Low Power technolo...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： S. Monfray F. Boeuf P. Coronel G. Bidal S. Denorme T. Skotnicki STMicroelectronics Private Limited Crolles France

The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices. This technology opens a wide range of applications, in particular for the realization of localized single-gate fully depleted transistors on bulk substrates and of double-gate planar devices, co-integrable with conventional bulk devices.

关键词： Silicon germanium Germanium silicon alloys Energy consumption Delay Capacitance CMOS technology Substrates High-K gate dielectrics Fabrication Nanoscale devices

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Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential —

Which is the best dual-port SRAM in 45-nm process technology...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Hiroki Noguchi Shunsuke Okumura Yusuke Iguchi Hidehiro Fujiwara Yasuhiro Morita Koji Nii Hiroshi Kawaguchi Masahiko Yoshimoto Kobe University Kobe Japan Renesas Technology Corporation Itami Japan

This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter and transmission gate are appended as a single-end read port. The readout power of the 10T single-end SRAM is reduced by 75% and the operating frequency is increased by 95%, over the 8T SRAM. On the other hand the 10T differential SRAM can operate fastest, because its small differential voltage of 50 mV achieves the high-speed operation. In terms of the power efficiency, however, the sense amplifier and precharge circuits lead to the power overhead. As a result, the 10T single-end SRAM always consumes lowest readout power compared to the 8T and the 10T differential SRAM.

关键词： Random access memory Frequency Voltage Inverters Power amplifiers Circuit topology Signal processing HDTV TV Video codecs

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