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文献详情 >HIRECS: HYPERCUBE IMPLEMENTATI... 收藏

HIRECS: HYPERCUBE IMPLEMENTATION OF RELAXATION-BASED CIRCUIT SIMULATION

作     者:SRILATA RAMAN L.M. PATNAIK 

作者机构:Dept. of Electrical and Computer Engineering and Coordinated Science Laboratory University of Illinois at Urbana-Champaign IL 61801 U.SA Dept. of Computer Science and Automation and Microprocessor Applications Laboratory Indian Institute of Science Bangalore 560 012 INDIA 

出 版 物:《International Journal of High Speed Computing》 

年 卷 期:1989年第1卷第3期

页      面:399-432页

主  题:Circuit simulation Hypercube architecture Parallel processing Waveform relaxation 

摘      要:Circuit simulation is a highly compute-intensive task as it involves solving thousands of ordinary differential equations (ODEs) describing the VLSI circuit under consideration. This paper describes an effort towards speeding up this task using a hypercube-based architecture. The paper focusses on the design and development of HIRECS (Hypercube Implementation of RElaxation-Based Circuit Simulation). HIRECS is based on the relaxation approach of solving the ODEs describing the circuit. The natural decomposition of the problem makes the relaxation algorithms amenable to parallel implementation. HIRECS employs the Waveform Relaxation (WR) algorithm. The special feature of WR algorithm is that the latency of the circuit can be exploited better, effecting a saving in the total computation time. The concept of ’windowing’ has been incorporated in HIRECS to effect a saving in the memory requirement. Another important feature of HIRECS is a novel synchronization scheme called partial synchronization. HIRECS runs on a DEC-1090 system and is developed using SIMULA. Performance studies of HIRECS based on parameters such as speedup, efficiency, and utilization of processors have been carried out. The performance evaluation of HIRECS in the simulation of some bench mark circuits like inverter chains and multiplexers indicates that a significant speedup, almost linear, can be obtained using a hypercube. For circuits with large number of nodes, such an implementation can result in tremendous saving in the computation time.

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