Machine Learning for VLSI Chip Design

版本说明：1

作     者：Abhishek Kumar Suman Lata Tripathi K. Srinivasa Rao 

I S B N：(纸本) 9781119910398 

出 版 社：Scrivener Publishing LLC 

出 版 年：2023年

主 题 词：VLSI Design Machine Learning Algorithm Neural Network VLSI Architecture Hardware Trojan Trojan Detection and Prevention FPGA SOC Hardware Accelerator Edge Accelerator 

学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

摘      要：MACHINE LEARNING TECHNIQUES FOR VLSI CHIP DESIGN This cutting-edge new volume covers the hardware architecture implementation, the software implementation approach, the efficient hardware of machine learning applications with FPGA or CMOS circuits, and many other aspects and applications of machine learning techniques for VLSI chip design. Artificial intelligence (AI) and machine learning (ML) have, or will have, an impact on almost every aspect of our lives and every device that we own. AI has benefitted every industry in terms of computational speeds, accurate decision prediction, efficient machine learning (ML), and deep learning (DL) algorithms. The VLSI industry uses the electronic design automation tool (EDA), and the integration with ML helps in reducing design time and cost of production. Finding defects, bugs, and hardware Trojans in the design with ML or DL can save losses during production. Constraints to ML-DL arise when having to deal with a large set of training datasets. This book covers the learning algorithm for floor planning, routing, mask fabrication, and implementation of the computational architecture for ML-DL. The future aspect of the ML-DL algorithm is to be available in the format of an integrated circuit (IC). A user can upgrade to the new algorithm by replacing an IC. This new book mainly deals with the adaption of computation blocks like hardware accelerators and novel nano-material for them based upon their application and to create a smart solution. This exciting new volume is an invaluable reference for beginners as well as engineers, scientists, researchers, and other professionals working in the area of VLSI architecture development.