An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

作     者：Iqbal, Muhammad Mazher Parvez, Husain Hussain, Fasahat Rashid, Muhammad 

作者机构：Karachi Inst Econ & Technol Karachi 75190 Pakistan Digitek Engn Karachi Pakistan Umm Al Qura Univ Coll Comp & Informat Syst Comp Engn Dept Mecca Saudi Arabia 

出 版 物：《JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS》 (电路、系统与计算机杂志)

年 卷 期：2021年第30卷第4期

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Application specific FPGA reconfigurable ASIC NPN SRAM-Table sharing field programmable gate array reconfiguration overheads 

摘      要：An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (Gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF++. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF++. It is found through experimental results that an ASIF++ is 4-9% area-efficient and requires 36% lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2-5 circuits. It also achieves 34-53% area saving as compared to a traditional FPGA.