Buffer Reduction Via N-Phase Clocking in Adiabatic Quantum-Flux-Parametron Benchmark Circuits

作     者：Saito, Ro Ayala, Christopher L. Yoshikawa, Nobuyuki 

作者机构：Yokohama Natl Univ Grad Sch Engn Sci Yokohama Kanagawa 2408501 Japan Yokohama Natl Univ Inst Adv Sci Yokohama Kanagawa 2408501 Japan Yokohama Natl Univ Dept Elect & Comp Engn Yokohama Kanagawa 2408501 Japan 

出 版 物：《IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY》 (IEEE应用超导汇刊)

年 卷 期：2021年第31卷第6期

页      面：1-8页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0702[理学-物理学] 

基　　金：Office of the Directory of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office [W911NF-17-1-0120] Japan Society for the Promotion of Science (JSPS) [19H05614, 18K13801] Grants-in-Aid for Scientific Research [18K13801] Funding Source: KAKEN 

主　　题：Logic gates Clocks Timing Superconducting logic circuits Superconducting integrated circuits Adiabatic Logic functions multi phase clocking retiming AQFP logic superconductor electronics logic synthesis 

摘      要：Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family capable of producing extremely low-energy computing systems. However, AQFP circuitry has some challenges to overcome before it can go into practical use, and improving circuit integration is one of them. Conventionally, a four-phase clocking distribution has been utilized as the power-clock network for AQFP circuits. This method requires gates to transmit data signal currents on adjacent phases. The drawback to four-phase clocking is not only the large latency due to limiting signal propagation to four-stages of logic in a single cycle, but also the enormous amount of signal buffering that is required for large circuits. Buffering uses up valuable area on the chip. We propose the adoption of an n-phase clocking method to not only reduce the latency of AQFP circuits but to also reduce the number of buffers for n larger than 4. When the number of phases per clock cycle increases by x times, we show that the number of buffers can be decreased to 1/x times in a number of AQFP benchmark circuits.