AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

作     者：Sohrabizadeh, Atefeh Yu, Cody Hao Gao, Min Cong, Jason 

作者机构：Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA Falcon Comp Inc 3979 Freedom Circle Suite 530 Santa Clara CA 95054 USA 

出 版 物：《ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS》 (美国计算机学会电子系统自动化设计汇刊)

年 卷 期：2022年第27卷第4期

页      面：32-32页

核心收录：

学科分类：08[工学] 0835[工学-软件工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：NSF [CCF-1723773, CNS-1719403] Intel [36888881, 34627365] CDSC industrial partners 

主　　题：Bottleneck optimizer customized computing HLS Merlin Compiler 

摘      要：Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS), accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. To address this problem, we propose an automated DSE framework-AutoDSE-that leverages a bottleneck-guided coordinate optimizer to systematically find a better design point. AutoDSE detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. The experimental results show that AutoDSE is able to identify the design point that achieves, on the geometric mean, 19.9x speedup over one CPU core for MachSuite and Rodinia benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx Vitis libraries, AutoDSE can reduce their optimization pragmas by 26.38x while achieving similar performance. With less than one optimization pragma per design on average, we are making progress towards democratizing customizable computing by enabling software programmers to design efficient FPGA accelerators.