版权所有:内蒙古大学图书馆 技术提供:维普资讯• 智图
内蒙古自治区呼和浩特市赛罕区大学西街235号 邮编: 010021
作者机构:Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau 999078 Peoples R China Univ Macau IME ECE FST Macau 999078 Peoples R China Univ Pavia Dept Elect I-27100 Pavia Italy Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal
出 版 物:《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 (IEEE J Solid State Circuits)
年 卷 期:2022年第57卷第5期
页 面:1358-1371页
核心收录:
基 金:Science and Technology Development Fund, Macau, SAR [FDCT 0036/2020/AGJ, SKL-AMSV (UM)-2020-2022] Guangzhou Science and Technology Innovation and Development of Special Funds (GSTIC) [EF002/IME-CY/2019/GSTIC]
主 题:Clocks Artificial neural networks Voltage-controlled oscillators Detectors Very large scale integration Time-frequency analysis Hardware Bang-bang clock and data recovery (BBCDR) charge pump (CP) CMOS four-level pulse-amplitude modulation (PAM) frequency detector (FD) half-rate negative net current (NNC) positive net current (PNC) reference-less and zero net current (ZNC)
摘 要:This article reports a half-rate single-loop bang-bang clock and data recovery (BBCDR) circuit without the need of reference and frequency detector (FD). Specifically, we propose a deliberate-current-mismatch charge-pump pair to enable fast and robust frequency acquisition without identifying the frequency error polarity. This technique eliminates the need for a complex high-speed data or clock path during the frequency acquisition, resulting in significant power savings. Prototyped in 28-nm CMOS, the BBCDR circuit automatically tracks a four-level pulse-amplitude modulation (PAM-4) input between 47.6 and 58.8 Gb/s. The core area is 0.056 mm(2). Both the achieved energy efficiency (0.22-0.25 pJ/bit) and the acquisition speed [9.8 (Gb/s)/mu s] compare favorably with the state of the art.