Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit

作     者：Lee, Yeji Jang, Wonyeong Kwon, Kyungbae Park, Jihun Yoo, Changhyun Chang, Jeesoo Jeon, Jongwook 

作者机构：Konkuk Univ Dept Elect & Elect Engn Seoul 05029 South Korea Samsung Elect Innovat Ctr Hwasung Si 16677 Gyeonggi Do South Korea 

出 版 物：《IEEE ACCESS》 (IEEE Access)

年 卷 期：2022年第10卷

页      面：80695-80702页

核心收录：

基　　金：National Foundation of Korea (NRF) - Korea Government [Ministry of Science and ICT (MSIT)] [2020M3F3A2A01081595  2020M3F3A2A01082326] 

主　　题：Integrated circuit modeling Wiring Resistance Layout Three-dimensional displays Metals Logic gates Gate-all-around FET process design kit parasitic extraction benchmark air spacer 

摘      要：With the continuous development of front-end-of-line (FEOL) technology, the development of interconnection processes at nanoscale process nodes is becoming important. We conducted a post-layout circuit simulation to consider the effect of parasitic R and C components of middle-of-Line (MOL) and back-end-of-line (BEOL) on the circuit performance. We constructed a process design kit (PDK) for path-finding to analyze the circuit layout in a 3nm technology node based on gate-all-around FET (GAA-FET). It consists of the spice model library that satisfies the 3nm power performance area (PPA) target, and the layout versus schematic (LVS), parasitic extraction (PEX) model that checks whether the layout and schematic match, extracts the RC values in the FEOL MOL and BEOL areas. Subsequently, the effect of the interconnection on complex logic circuits (RO, full adder) was confirmed using PDK. As a result of quantifying the effects of FEOL, MOL, and BEOL on the circuit, circuit degradation due to the RC of MOL and BEOL accounts for more than 60%. Furthermore, we introduced the air spacer process as a way to improve the circuit performance by reducing the C-MOL owing to the reduction in the dielectric constant of the spacer. When an air spacer is introduced, based on 9-stages FO1 INV RO with k = 7 at V-DD = 0.7V, under iso-speed condition, the active power decreases by 30%, 35% when k is 3.3, 1.65, respectively. Under iso-power condition, frequency increases by 9%, 11% when k is 3.3, 1.65, respectively. And based on full adder with k = 7 at V-DD = 0.7V, Under iso-speed conditions, the active power decreases by 47%, 58% when k is 3.3, 1.65, respectively. Under iso-power conditions, the delay decreases by 14%, 20% when k is 3.3, 1.65, respectively. PDP decreases by 22%, 32% when k is 3.3, 1.65, respectively. EDP decreases by 31%, 44% when k is 3.3, 1.65, respectively. In conclusion, in this work, we provide a guide for determining the BEOL load and developing an improved wiring p