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作者机构:State Key Laboratory of Advanced Optical Communication Systems and Networks Shanghai Jiao Tong University Shanghai200240 China
出 版 物:《SSRN》
年 卷 期:2022年
核心收录:
主 题:Field programmable gate arrays (FPGA)
摘 要:Physical-layer secure key distribution (PLSKD) provides robust security and full compatibility with current fiber infrastructure. The post-processing is generally required to improve the key consistency, security, and randomness in PLSKD. However, offline digital signal processing was generally adopted in the previous PLSKD schemes, while the real-time post-processing is necessary towards the practical PLSKD applications. In this paper, a real-time pipeline post-processing is designed and demonstrated using field-programmable gate array (FPGA) boards. A complete set of post-processing is applied, including: double-threshold quantization, information reconciliation with Bose-Chaudhuri-Hocquenghem code, and privacy amplification with SM3 hash algorithm. The system architecture is detailed by combining all these processing steps, where the trade-offs for the post-processing scheme are analyzed. We also assess the performance of post-processing implementation on FPGA in terms of throughput and hardware resource utilization. On the FPGA platform, the final key rate is up to 12.2 Mb/s. The proposed real-time post-processing FPGA prototype is a good candidate for the practical application of PLSKD in fiber networks. © 2022, The Authors. All rights reserved.