Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File

作     者：Kashima, Ryota Nagaoka, Ikki Nakano, Tomoki Tanaka, Masamitsu Yamashita, Taro Fujimaki, Akira 

作者机构：Nagoya Univ Dept Elect Nagoya 4648603 Japan Tohoku Univ Dept Appl Phys Sendai 9808577 Japan 

出 版 物：《IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY》 (IEEE Trans Appl Supercond)

年 卷 期：2023年第33卷第5期

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0702[理学-物理学] 

基　　金：JSPS KAKENHI [JP18H05211, JP19H01105, JP18H01498] JST MIRAI [JPMJMI18E1] 

主　　题：Radio frequency Clocks Pipelines Microprocessors Throughput Logic gates Delays Bit-parallel processing gate-level-pipeline microprocessor single-flux-quantum logic 

摘      要：In this paper, we successfully demonstrate the 50-GHz operation of a microprocessor datapath based on single-flux -quantum (SFQ) logic with a gate-level pipeline (GLP) structure. The microprocessor datapath features a register file (RF), an arithmetic logic unit (ALU), and a long feedback loop that connects these components. Interleaved data-processing is applied in the RF. As the operating frequency of the RF is half that of the ALU, the timing constraints are eased;thus, we can reduce the number of pipeline stages used for timing adjustments. We designed a 4-bit datapath using the proposed technique, targeting 50-GHz opera-tion. Compared to the conventional datapath, the total number of pipeline stages and the latency decreased from 49 to 24 and from 980 to 760 ps respectively. We fabricated test chips using the AIST Nb 9-layer 10-kA/cm(2) process, and performed successful on-chip high-speed tests. In addition, our preliminary experiments suggest that we can expect 1.6-fold higher throughput at an 80-GHz clock frequency, at the cost of a 10% increase in latency.