An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method

作     者：Jia, Xiaotao Gu, Huiyi Liu, Yuhao Yang, Jianlei Wang, Xueyan Pan, Weitao Zhang, Youguang Cotofana, Sorin Zhao, Weisheng 

作者机构：Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Beihang Hangzhou Innovat Inst Yuhang Hangzhou 310023 Peoples R China Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China Beihang Univ Sch Comp Sci & Engn BDBC Beijing 100191 Peoples R China Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China Delft Univ Technol Comp Engn Lab NL-2628 CD Delft Netherlands 

出 版 物：《IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS》 (IEEE Trans. Neural Networks Learn. Sys.)

年 卷 期：2024年第35卷第9期

页      面：12913-12923页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：National Natural Science Foundation of China [62006011, U20A20204, 62072019, 62004011] 111 Talent Program [B16001] 

主　　题：Neural networks Standards Bayes methods Hardware Training Uncertainty Integrated circuit modeling Bayesian neural network (BNN) energy efficiency Gaussian random number generator stochastic computing (SC) 

摘      要：The robustness of Bayesian neural networks (BNNs) to real-world uncertainties and incompleteness has led to their application in some safety-critical fields. However, evaluating uncertainty during BNN inference requires repeated sampling and feed-forward computing, making them challenging to deploy in low-power or embedded devices. This article proposes the use of stochastic computing (SC) to optimize the hardware performance of BNN inference in terms of energy consumption and hardware utilization. The proposed approach adopts bitstream to represent Gaussian random number and applies it in the inference phase. This allows for the omission of complex transformation computations in the central limit theorem-based Gaussian random number generating (CLT-based GRNG) method and the simplification of multipliers as and operations. Furthermore, an asynchronous parallel pipeline calculation technique is proposed in computing block to enhance operation speed. Compared with conventional binary radix-based BNN, SC-based BNN (StocBNN) realized by FPGA with 128-bit bitstream consumes much less energy consumption and hardware resources with less than 0.1% accuracy decrease when dealing with MNIST/Fashion-MNIST datasets.