Design and Research of Improved Digital Phase-Locked Loop Based on FPGA

作     者：Junming Ye Guangxiang Zhou Haiyan Liu 

作者机构：Guilin University of Electronic TechnologyGuilin 54100GuangxiChina 

出 版 物：《Procedia Engineering》 (工程学会议集)

年 卷 期：2012年第29卷

页      面：547-552页

学科分类：12[管理学] 1201[管理学-管理科学与工程(可授管理学、工学学位)] 08[工学] 

主　　题：Digital Phase - Locked Loop Complex programmable logic device Verilog 

摘      要：In order to improve anti-jamming performance of the sensor, fast lock digital PLL is proposed and the PLL is used in the sensor. Digital PLL with a simple structure, flexible control, high tracking accuracy, loop performance and easy integration of features; while PLL loop automatic variable in the model control technology to speed up the rate locked loop to reduce Phase jitter. In this paper, the arithmetic average and moving average value of the software filter scheme to solve the sensor can filter out high frequency interference filter design problems and improve robustness.