MARSELLUS: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing

作     者：Conti, Francesco Paulin, Gianna Garofalo, Angelo Rossi, Davide Mauro, Alfio Di Rutishauser, Georg Ottavi, Gianmarco Eggimann, Manuel Okuhara, Hayate Benini, Luca 

作者机构： University of Bologna Bologna40126 Italy The Integrated Systems Laboratory ETH Zürich Zürich8092 Switzerland Department of Electrical and Computer Engineering National University of Singapore Singapore The University of Bologna Italy The University of Bologna Bologna40126 Italy ETH Zürich Zürich8092 Switzerland 

出 版 物：《arXiv》 (arXiv)

年 卷 期：2023年

核心收录：

主　　题：Deep neural networks 

摘      要：Emerging Artificial Intelligence-enabled Internet-of-Things (AI-IoT) System-on-a-Chips (SoCs) for augmented reality, personalized healthcare, and nano-robotics need to run many diverse tasks within a power envelope of a few tens of mW over a wide range of operating conditions: compute-intensive but strongly quantized Deep Neural Network (DNN) inference, as well as signal processing and control requiring high-precision floating-point. We present MARSELLUS, an all-digital heterogeneous SoC for AI-IoT end-nodes fabricated in GlobalFoundries 22nm FDX that combines 1) a general-purpose cluster of 16 RISC-V digital signal processing (DSP) cores attuned for the execution of a diverse range of workloads exploiting 4-bit and 2-bit arithmetic extensions (XpulpNN), combined with fused MAC&LOAD operations and floating-point support;2) a 2-8bit Reconfigurable Binary Engine (RBE) to accelerate 3×3 and 1×1 (pointwise) convolutions in DNNs;3) a set of On-Chip Monitoring (OCM) blocks connected to an Adaptive Body Biasing (ABB) generator and a hardware control loop, enabling on-the-fly adaptation of transistor threshold voltages. MARSELLUS achieves up to 180 Gop/s or 3.32 Top/s/W on 2-bit precision arithmetic in software, and up to 637 Gop/s or 12.4 Top/s/W on hardware-accelerated DNN layers. Copyright © 2023, The Authors. All rights reserved.