Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes

作     者：Choi, Moonjeong Park, Juhwan Choi, Seoungyeol Kwon, Kyungbae Lee, Yeji Jang, Wonyeong Jeon, Jongwook 

作者机构：Konkuk Univ Dept Elect & Elect Engn Seoul 05029 South Korea Sungkyunkwan Univ Sch Elect & Elect Engn Suwon 16419 South Korea 

出 版 物：《JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE》 (J. Semicond. Technol. Sci.)

年 卷 期：2023年第23卷第4期

页      面：215-227页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0702[理学-物理学] 

基　　金：National Foundation of Korea (NRF) - Korea government (MSIT) [2022M3F3A2A01072215] National Foundation of Korea(NRF) - Korea government (MSIT) [2021M3F3A2A03017693] 

主　　题：Gate-all-around FET process design kit parasitic extraction benchmark interconnect 

摘      要：In this work, circuit-level benchmarks were performed on Copper(Cu), Tungsten(W), Cobalt(Co), Ruthenium(Ru), and Doped-multilayer-graphene (DMLG), which are various metallic material options applicable to the wire process at the late semiconductor process nodes. For the transistor, a multi-nanosheet field-effect-transistor (mNS-FET) with gate-all-around (GAA) technology was used, and the power and performance characteristics of the inverter ring oscillator circuit were analyzed assuming a 3 nm process node. In addition, various wire metal options for circuit layout were evaluated by varying fan-out number and wire length. As a result, the speed is fastest for Co and the speed reduction is smallest for DMLG in FO1 50CPP.