Performance assessment of a new reduced component multilevel inverter with discrete modulation techniques

作     者：Karri, Krishna Kumari Singh, Varsha Pattnaik, Swapnajit 

作者机构：Department of Electrical Engineering National Institute of Technology Raipur India 

出 版 物：《International Journal of Power Electronics》 (Intern. J. Power. Electron.)

年 卷 期：2024年第19卷第3-4期

页      面：221-245页

核心收录：

学科分类：1201[管理学-管理科学与工程(可授管理学、工学学位)] 0809[工学-电子科学与技术（可授工学、理学学位）] 081203[工学-计算机应用技术] 08[工学] 081402[工学-结构工程] 0835[工学-软件工程] 0813[工学-建筑学] 0814[工学-土木工程] 0701[理学-数学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Efficiency 

摘      要：Multilevel inverter (MLI) has been widely used in industrial applications over the last few decades, however economical MLI design with compatible pulse width modulation needs attention. This paper proposes a new MLI with three sources and eight switches, producing seven and a maximum of 11 levels with symmetrical and asymmetrical DC sources. Novel topology features are lesser component count, fewer DC-link switches, lower total standing voltage, and cost function. A comparative analysis of the proposed configuration with existing topologies is presented for single and cascaded connections of multiple modules. Further, discrete modulation approaches are used to investigate the influence of modulation index variation on the proposed inverter’s output voltage, total harmonics distortion, power, and efficiency while considering static and dynamic load changes. The performance of MLI with optimised staircase modulation using PSO technique surpasses high-frequency multi-carrier level shift modulation methods. Extensive simulation tests are carried out in MATLAB and validated with experimental results. Copyright © 2024 Inderscience Enterprises Ltd.