Implementation of a Boolean function with a double-gate vertical TFET (DGVTFET) using numerical simulations

作     者：Mathew, Ribu Beohar, Ankur Ghosh, Jyotirmoy Sarkar, Pallabi Upadhyay, Abhishek Kumar 

作者机构：Manipal Acad Higher Educ MAHE Manipal Sch Informat Sci MSIS Udupi 576104 Karnataka India VIT Bhopal Univ Sch Elect & Elect Engn SEEE Bhopal 466114 India XFAB GmbH Grenzstr 28 D-01109 Dresden Germany 

出 版 物：《JOURNAL OF COMPUTATIONAL ELECTRONICS》 (计算电子学杂志)

年 卷 期：2024年第23卷第3期

页      面：525-532页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0702[理学-物理学] 

基　　金：SERB TARE GRANT  Govt. of India 

主　　题：Boolean function Field-effect transistor (FET) Scaling Double-gate vertical TFET (DGVTFET) ON/OFF current ratio Short-channel effect (SCE) 

摘      要：Tunnel field-effect transistors (TFETs) have been explored extensively as a possible substitute for MOSFETs, especially for digital system design applications. Unlike conventional MOSFET devices, TFETs exhibit certain unique characteristics which are suitable for energy-efficient digital system design. In this paper, we report the use of a single device with both terminals biased independently for basic two-input Boolean logic operations AND, OR, NAND, and NOR using technology computer-aided design (TCAD) simulations. It is shown that these basic Boolean operations can be realized by minimally altering the design of a double-gate vertical TFET (DGVTFET) device and by selecting the appropriate device characteristics. The results show that when the Boolean functions are implemented, the ION/IOFF ratio is in the range of 109 to 1013 at a supply voltage VDD = 1 V. Simulation results show that the use of a gate-source overlap technique and the selection of a suitable silicon body thickness are vital to obtaining distinct logic functions using a DGVTFET.