Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors

作     者：Kadyrzhan, Aruzhan Kadyrzhan, Kaisarali Bakirov, Akhat Suleimenov, Ibragim 

作者机构：Gumarbek Daukeev Almaty Univ Power Engn & Commun Inst Commun & Space Engn Dept Telecommun Engn Alma Ata 050040 Kazakhstan Natl Engn Acad Republ Kazakhstan Alma Ata 050010 Kazakhstan 

出 版 物：《APPLIED SCIENCES-BASEL》 (Appl. Sci.)

年 卷 期：2025年第15卷第2期

页      面：741-741页

核心收录：

基　　金：Science Committee of the Ministry of Higher Education and Science of the Republic of Kazakhstan AP23490107 

主　　题：quasi-Mersen numbers trigger adder effective bit depth of adder computing performance parallel-serial computing residue number system (RNS) 

摘      要：It is shown that a serial-parallel processor, comparable in bit capacity to a 16-bit binary processor, can be implemented based on an algorithm built on the residue number system, a distinctive feature of which is the use of the first four quasi-Mersenne numbers, i.e., prime numbers representable as pk=2k+1, k=1,2,3,4. Such a set of prime numbers satisfies the criterion 2p1p2p3p4+1=P, where P is also a prime number. Fulfillment of this criterion ensures the possibility of convenient use of the considered RNS for calculating partial convolutions developed for the convenience of using convolutional neural networks. It is shown that the processor of the proposed type can be based on the use of a set of adders modulo a quasi-Mersenne number, each of which operates independently. A circuit of a modulo 2k+1 adder is proposed, which can be called a trigger circuit, since its peculiarity is the existence (at certain values of the summed quantities) of two stable states. The advantage of such a circuit, compared to known analogs, is the simplicity of the design. Possibilities for further development of the proposed approach related to the use of the digital logarithm operation, which allows reducing the operations of multiplication modulo 2k+1 to addition operations, are discussed.