P3DC:Reducing DRAM Cache Hit Latency by Hybrid Mappings

作     者：Ye Chi Ren-Tong Guo Xiao-Fei Liao Hai-Kun Liu Jianhui Yue 池也;郭人通;廖小飞;刘海坤;岳建辉

作者机构：National Engineering Research Center for Big Data Technology and SystemWuhan 430074China Services Computing Technology and System LaboratoryWuhan 430074China Cluster and Grid Computing LaboratoryWuhan 430074China School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China School of Big Data and InternetShenzhen Technology UniversityShenzhen 518118China Department of Computer ScienceMichigan Technological UniversityHoughton 49931-1295U.S.A. 

出 版 物：《Journal of Computer Science & Technology》 (计算机科学技术学报(英文版))

年 卷 期：2024年第39卷第6期

页      面：1341-1360页

核心收录：

学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported jointly by the National Key Research and Development Program of China under Grant No.2022YFB4500303 the National Natural Science Foundation of China under Grant Nos.62072198,61825202,and 61929103 

主　　题：die-stacked dynamic random access memory(DRAM) cache set-associative direct-mapped hit latency 

摘      要：Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main *** fully realize their potential,it is essential to improve DRAM cache hit rate and lower its cache hit *** order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time,we propose a partial direct-mapped die-stacked DRAM cache called *** design is motivated by a key observation,i.e.,applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency *** address this problem,P3DC classifies data blocks into leading blocks and following blocks,and places them at static positions and dynamic positions,respectively,in a unified set-associative *** also propose a replacement policy to balance the miss penalty and the temporal locality of different *** addition,P3DC provides a policy to mitigate cache thrashing due to block type *** results demonstrate that P3DC can reduce the cache hit latency by 20.5%while achieving a similar cache hit rate compared with typical set-associative caches.P3DC improves the instructions per cycle(IPC)by up to 66%(12%on average)compared with the state-of-the-art direct-mapped cache—BEAR,and by up to 19%(6%on average)compared with the tag-data decoupled set-associative cache—DEC-A8.