Parallelized Field-Programmable Gate Array Data Processing for High-Throughput Pulsed-Radar Systems

作     者：Pitcher, Aaron D. Georgiev, Mihail Nikolova, Natalia K. Nicolici, Nicola 

作者机构：McMaster Univ Electromagnet Vis EMVi Res Lab Hamilton ON L8S 4L8 Canada McMaster Univ Comp Aided Design & Test CADT Res Grp Hamilton ON L8S 4L8 Canada 

出 版 物：《SENSORS》 (Sensors)

年 卷 期：2025年第25卷第1期

页      面：239页

核心收录：

学科分类：0710[理学-生物学] 071010[理学-生物化学与分子生物学] 0808[工学-电气工程] 07[理学] 0804[工学-仪器科学与技术] 0703[理学-化学] 

基　　金：Defence and Security Accelerator (DASA) [DSTLX1000147682] Defence and Security Accelerator (DASA) program (Ministry of Defence, UK) [G4992] Science for Peace and Security (SPS) program (NATO) [6636-547551-2020, RGPIN-2023-04483] Natural Sciences and Engineering Research Council (NSERC) of Canada 

主　　题：concealed weapon detection field-programmable gate array equivalent-time sampling subsampling ultra-wideband measurement techniques ultra-wideband radar 

摘      要：A parallelized field-programmable gate array (FPGA) architecture is proposed to realize an ultra-fast, compact, and low-cost dual-channel ultra-wideband (UWB) pulsed-radar system. This approach resolves the main shortcoming of current FPGA-based radars, namely their low processing throughput, which leads to a significant loss of data provided by the radar receiver. The architecture is integrated with an in-house UWB pulsed radar operating at a sampling rate of 20 gigasamples per second (GSa/s). It is demonstrated that the FPGA data-processing speed matches that of the radar output, thus eliminating data loss. The radar system achieves a remarkable speed of over 9000 waveforms per second on each channel. The proposed architecture is scalable to accommodate higher sampling rates and various waveform periods. It is also multi-functional since the FPGA controls and synchronizes two transmitters and a dual-channel receiver, performs signal reconstruction on both channels simultaneously, and carries out user-defined averaging, trace windowing, and interference suppression for improving the receiver s signal-to-noise ratio. We also investigate the throughput rate while offloading radar data onto an external device through an Ethernet link. Since the radar data rate significantly exceeds the Ethernet link capacity, we show how the FPGA-based averaging and windowing functions are leveraged to reduce the amount of offloaded data while fully utilizing the radar output.