A PARALLEL ARCHITECTURE FOR RELAXATION OPERATIONS

作     者：KAMADA, M TORAICHI, K MORI, R YAMAMOTO, K YAMADA, H 

作者机构：UNIV TSUKUBAINST INFORMAT SCI & ELECTR1-1 TEN NOUDAISAKURAIBARAKI 305JAPAN UNIV TSUKUBADOCTORAL PROGRAM ENGNSAKURAIBARAKI 305JAPAN MINIST INT TRADE & INDELECTROTECH LABSAKURAIBARAKI 305JAPAN 

出 版 物：《PATTERN RECOGNITION》 (Pattern Recogn.)

年 卷 期：1988年第21卷第2期

页      面：175-181页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Relaxation method Parallel architecture Round-robin structure Handwritten character recognition Very large scale integration (VLSI) 

摘      要：Relaxation method attracts attention as an effective parallel method in image processing and pattern recognition. But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.