System-Level Application of the Z-Directed Component (ZDC) for Power Integrity

作     者：Vuppunutala, Pranay Zhu, Xiaolu Park, Junyong Hardin, Keith B. Kratzer, Zachary C. N. Fessler, John T. Zhao, Biyao Bai, Siqi 

作者机构：Missouri University of Science and Technology Electromagnetic Compatibility Laboratory RollaMO65401 United States Dankook University Yongin16890 Korea Republic of Lexmark International Inc. LexingtonKY40550 United States 

出 版 物：《IEEE Transactions on Signal and Power Integrity》 (IEEE. Trans. Signal. Power. Integr.)

年 卷 期：2025年第4卷

页      面：10-18页

核心收录：

基　　金：National Science Foundation 

主　　题：Surface mount technology 

摘      要：The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integrated circuits (ICs) to mitigate the noise inherent with switching. A new technology capacitor, Z-directed component (ZDC), can target printed circuit board (PCB) component locations at the package balls of the IC through the PCB. A commercially available PCB PDN design, using a conventional surface mount technology (SMT) decoupling solution, was analyzed utilizing a commercially available simulation-based tool and validated by impedance measurements. The ZDC PDN performance in the system was predicted by substituting a ZDC capacitor model for selected SMT capacitors. The validation was carried out using two-port PDN measurements on the PCB. Finally, an equivalent circuit model is developed using cavity model and plane-pair partial element equivalent circuit techniques to represent the physics associated with current paths from all the decoupling capacitors to the IC. The simulation results from a commercial tool are corroborated with both the measurements and an equivalent circuit model. It is demonstrated that opting for ZDC as a decoupling solution can deliver significantly lower impedances as compared to the SMT solution for this design. Thus, the ZDC approach is a promising decoupling solution for future power integrity applications, enhancing the power integrity performance of the system, facilitating the use of cost-effective lower layer count PCBs for much higher speeds than adopting an SMT strategy. © 2022 IEEE.