14-Bit SAR ADC with on-Chip Digital Bubble Sorting Calibration Technology

作     者：Hua Fan Zhuorui Chen Tongrui Xu Franco Maloberti Qi Wei Quanyuan Feng Fan Hua;Chen Zhuorui;Xu Tongrui;Maloberti Franco;Wei Qi;Feng Quanyuan

作者机构：School of Integrated Circuit Science and Engineering(Exemplary School of Microelectronics) University of Electronic Science and Technology of China Shenzhen Institute for Advanced Study University of Electronic Science and Technology of China Chongqing Institute of Microelectronics Industry Technology University of Electronic Science and Technology of China Department of Electrical Computer and Biomedical Engineering University of Pavia Department of Precision Instrument Tsinghua University Institute of Microelectronics Southwest Jiaotong University 

出 版 物：《Chinese Journal of Electronics》 (电子学报(英文))

年 卷 期：2025年第34卷第1期

页      面：125-136页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by the National Natural Science Foundation of China (Grant No. 62371109) in part by the Sichuan Science and Technology Program (Grant No. 2022YFG0164) in part by the Medico-Engineering Cooperation Funds from University of Electronic Science and Technology of China (Grant No. ZYGX2021YGLH203) in part by the General Project of Chongqing Natural Science Foundation (Grant No. 2022NSCQ-MSX5348) in part by the Guangdong Basic and Applied Basic Research Foundation (Grant No. 2023A1515010041) supported by the Major Project of the National Natural Science Foundation of China (Grant No. 62090012) 

主　　题：Semiconductor device measurement Capacitors Linearity Switches Calibration System-on-chip Frequency measurement Time-domain analysis Sorting Signal to noise ratio 

摘      要：This article designs a 14-bit successive approximation register analog-to-digital converter（SAR ADC）.A novel digital bubble sorting calibration method is proposed and applied to eliminate the effect of capacitor mismatch on the linearity of the SAR ADC. To reduce the number of capacitors, a hybrid architecture of a high 8-bit binary-weighted capacitor array and a low 6-bit resistor array is adopted by the digital-to-analog（DAC）. The common-mode voltage VCM-based switching scheme is chosen to reduce the switching energy and area of the DAC. The time-domain comparator is employed to obtain lower power consumption. Sampling is performed through a gate voltage bootstrapped switch to reduce the nonlinear errors introduced when sampling the input signal. Moreover, the SAR logic and the whole calibration is totally implemented on-chip through digital integrated circuit（IC） tools such as design compiler, IC compiler, etc. Finally, a prototype is designed and implemented using 0.18 μm bipolar-complementary metal oxide semiconductor（CMOS）-double-diffused MOS 1.8 V CMOS technology. The measurement results show that the SAR ADC with on-chip bubble sorting calibration method achieves the signal-to-noise-and-distortion ratio of 69.75 dB and the spurious-free dynamic range of 83.77 dB.