A WIP Balancing Procedure for Throughput Maximization in Semiconductor Fabrication

作     者：Chung, Jaewoo Jang, Jaejin 

作者机构：Purdue Univ Sch Ind Engn W Lafayette IN 47906 USA Univ Wisconsin Dept Ind & Mfg Engn Milwaukee WI 53211 USA 

出 版 物：《IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING》 (IEEE Trans Semicond Manuf)

年 卷 期：2009年第22卷第3期

页      面：381-390页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0802[工学-机械工程] 0702[理学-物理学] 

主　　题：Fabrication load balancing mixed integer programming scheduling semiconductor WIP balancing 

摘      要：In a semiconductor fabrication line (fab), high throughput often guarantees high revenue and profit since relatively constant operating cost is required throughout the year;however, maintaining high throughput has been a challenging task due to complicated operational variables in a modern high-end wafer fabrication line. To deal these variables, the industry has developed a fab scheduling system consisting of several functional modules that focus on different areas of decision making. WIP balancing, which aims to prevent starvation of bottleneck toolsets, has been an important component for fab scheduling. This research proposes a new WIP balancing concept, which directly considers load levels of bottleneck toolsets for higher throughput. Also, an MIP (mixed integer programming) model is developed for the new WIP balancing. A performance test shows that the new approach increases throughput, especially when WIP level and product routing flexibility are low.