Optimal decoupling capacitor sizing and placement for standard-cell layout designs

作     者：Su, HH Sapatnekar, SS Nassif, SR 

作者机构：IBM Corp Austin Res Lab Austin TX 78758 USA Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA 

出 版 物：《IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS》 (IEEE Trans Comput Aided Des Integr Circuits Syst)

年 卷 期：2003年第22卷第4期

页      面：428-436页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Scientific Research Council, (99-TJ-714) National Science Foundation, NSF, (CCR-0098117) National Science Foundation, NSF 

主　　题：application specific integrated circuits (ASIC) decoupling capacitor design automation nonlinear programming power distribution sensitivity 

摘      要：With technology scaling, the trend for high-performance integrated circuits is toward ever higher operating frequency, lower power supply voltages, and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in application specific integrated circuit (ASIC)-like circuits. The problem is formulated as one of nonlinear optimization and is solved using a sensitivity-based quadratic programming (QP) solver. The adjoint sensitivity method is applied to calculate the first-order sensitivities. We propose a fast convolution technique based on piecewise linear, (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change in the total chip area.