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作者机构:Politecn Torino Dipartimento Automat & Informat I-10129 Turin Italy Univ Bologna Dipartimento Elettron Informat & Sistemist I-40136 Bologna Italy
出 版 物:《IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS》 (IEEE Trans Comput Aided Des Integr Circuits Syst)
年 卷 期:2006年第25卷第12期
页 面:2626-2637页
核心收录:
学科分类:0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术(可授工学、理学学位)]
主 题:binary decision diagrams (BDDs) cache memory design automation embedded systems indexing algorithms memory hierarchy
摘 要:The predictability of memory access patterns in embedded systems can be successfully exploited to devise effective application-specific cache optimizations. In this paper, an improved indexing scheme for direct-mapped caches, which drastically reduces the number of conflict misses by using application-specific information, is proposed. The indexing scheme is based on the selection of a subset of the address bits. With respect to similar approaches, the solution has two main strengths. First, owing to an analytical model for the conflict-miss conditions of a given trace, it provides a symbolic algorithm to compute the optimum solution (i.e., the subset of address bits to be used as cache index that minimize the number of conflict misses). Second, owing to a reconfigurable bit selector that can be programmed at run time, it allows the optimal cache indexing to fit to a given application. Results show an average reduction of conflict misses of 24%, measured over a set of standard benchmarks, and for different cache configurations.