FPGA-specific decimal sign-magnitude addition and subtraction

作     者：Vazquez, Martin Todorovich, Elias 

作者机构：Univ Nacl Ctr Prov Buenos Aires Fac Ciencias Exactas Tandil Argentina FASTA Univ Fac Engn Mar Del Plata Argentina 

出 版 物：《INTERNATIONAL JOURNAL OF ELECTRONICS》 (国际电子学杂志)

年 卷 期：2016年第103卷第7期

页      面：1166-1185页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：Agencia Nacional de Promocion Cientifica y Tecnologica  Argentina [PICT 2009-0041] 

主　　题：sign-magnitude programmable logic IEEE 754-2008 Carry-chain decimal arithmetic 

摘      要：The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet performance constraints in some applications and more development is required in programmable logic, a key technology for hardware acceleration. Thus, in this work, two strategies for SM decimal adder/subtractors are studied and six new Field Programmable Gate Array (FPGA)-specific circuits are derived from these strategies. The first strategy is based on ten s complement (C10) adder/subtractors and the second one is based on parallel computation of an unsigned adder and an unsigned subtractor. Four of these alternative circuits are useful for at least one area-time-trade-off and specific operand size. For example, the fastest SM adder/subtractor for operand sizes of 7 and 16 decimal digits is based on the second proposed strategy with delays of 3.43 and 4.33 ns, respectively, but the fastest circuit for 34-digit operands is one of the three specific implementations based on C10 adder/subtractors with a delay of 4.65 ns.