Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

作     者：Guangyi LU Yuan WANG Lizhong ZHANG Jian CAO Xing ZHANG 

作者机构：Key Laboratory of Microelectronie Devices and Circuits(MoE)Institute of MicroelectronicsPeking UniversityBeijing 100871China 

出 版 物：《Science China Earth Sciences》 (中国科学（地球科学英文版）)

年 卷 期：2016年第59卷第12期

页      面：166-174页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported by National Science and Technology Major Project of China(Grant No.2013ZX02303002) 

主　　题：electrostatic discharge （ESD） power-rail ESD clamp circuit detection mechanism transient-noise immunity false triggering transmission line pulsing （TLP） test 

摘      要：This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit(TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current(Ileak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.