Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA

作     者：Zhang, Hao Chen, Dongdong Ko, Seok-Bum 

作者机构：Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK S7N 5A9 Canada Intel Corp San Jose CA USA 

出 版 物：《IET COMPUTERS AND DIGITAL TECHNIQUES》 (IET Comput. Digital Tech.)

年 卷 期：2017年第11卷第4期

页      面：149-158页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Natural Sciences and Engineering Research Council of Canada (NSERC) Department of Electrical and Computer Engineering at the University of Saskatchewan 

主　　题：field programmable gate arrays floating point arithmetic iterative methods floating-point multiplication field programmable gate array DSP blocks power-efficient iterative FP multiplier architecture single-precision operations double-precision operations Karatsuba algorithm pipeline registers Virtex-5 devices Altera Arria-10 devices Xilinx Virtex-7 ASIC platform 

摘      要：In this study, an area and power-efficient iterative floating-point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single-precision (SP) and double-precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look-up tables (LUTs), and 31.2% less flip-flops while having 4% faster clock frequency on Virtex-5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower-power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex-7 and Altera Arria-10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM-90 nm ASIC platform are reported.