High-speed and low-power CMOS priority encoders

作     者：Wang, JS Huang, CH 

作者机构：Natl Chung Cheng Univ Inst Elect Engn Chiayi 621 Taiwan 

出 版 物：《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 (IEEE J Solid State Circuits)

年 卷 期：2000年第35卷第10期

页      面：1511-1514页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

主　　题：Domino CMOS priority encoder 

摘      要：The design of two high-performance priority encoders is presented. The key techniques for high speed are twofold. First, a multilevel look-ahead structure is developed to shorten the critical path effectively Second, this look-ahead structure is realized efficiently by the NP Domino CMOS logic, and all the dynamic gates have a parallel-connected circuit structure. For high speed and low power at the same time, the series-connected circuit structure is adopted in the less critical paths to reduce the switching activity, but such a design needs to cascade two n-type dynamic gates directly resulting in the race problem. A special circuit technique is utilized to rescue this problem. Several 32-bit priority encoders are designed to evaluate the feasibility of the proposed techniques. The best new design realizes a three-level look-ahead structure, and it achieves 65% speed improvement, 20% layout area reduction, and 30% power reduction simultaneously as compared to the conventional design [1] with a simple look-ahead structure.