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内蒙古自治区呼和浩特市赛罕区大学西街235号 邮编: 010021
作者机构:Univ Engn & Technol Fac Elect & Elect Engn Dept Elect Engn Taxila Pakistan Natl Univ Sci & Technol Dept Elect Engn Islamabad Pakistan
出 版 物:《TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES》 (土耳其电机工程与计算机科学杂志)
年 卷 期:2018年第26卷第4期
页 面:1820-1832页
核心收录:
学科分类:080801[工学-电机与电器] 0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术(可授工学、理学学位)]
主 题:Self-mixing laser sensors real time phase unwrapping method direct fringe unwrapping improved direct fringe unwrapping field-programmable gate array
摘 要:Optical feedback interferometer (OFI) lasers, also called self-mixing (SM) lasers, have been widely explored over the last couple of decades due to their low cost, compactness, and self-aligned nature and they provide a very good solution for measurements of displacement, vibration, distance, velocity, etc. The SM effect takes place when a part of the laser beam is fed back to the active laser cavity after reflecting from the target. The reflected beam interferes with the emitted beam and hence the optical and spectral characteristics of the laser get changed. To retrieve the vibration or displacement signal of the target from the SM signal, different postprocessing algorithms have been proposed, such as the phase unwrapping method (PUM). The first step of the PUM leads to the coarse estimation of the laser phase and the final step is an iterative joint estimation of 2 parameters, namely laser coupling coefficient C and linewidth enhancement factor alpha. To make this algorithm applicable for real-time measurements, parallel joint estimation for a wide range of C and alpha values needs to be done. In this research, 3 algorithms, namely PUM, direct fringe unwrapping (DFU), and improved DFU (IDFU) were tested for FPGA implementation by using Verilog HDL (hardware description language) so that more precise and real-time vibration and displacement signals of targets could be extracted from the SM sensor in an embedded systems environment. These algorithms were developed using Verilog HDL for implementation on the Xilinx Spartan-3 Xcs400-FG320 development board. Our designed IDFU algorithm performed 0:492 times better than the parallel PUM algorithm in maximum clock frequency and 1:53 and 1:21 times better than the PUM in slice registers and LUT utilization of hardware resources, respectively. The designed DFU algorithm can operate 1:355 times better than IDFU in maximum clock frequency and 25:34 and 14:25 times better than IDFU in slice registers and LUT utilization of