Design and evaluation of system-level checks for on-line control flow error detection

作     者：Alkhalifa, Z Nair, VSS Krishnamurthy, N Abraham, JA 

作者机构：So Methodist Univ Dept Comp Sci & Engn Dallas TX 75275 USA Motorola PowerPC Design Ctr Austin TX USA Univ Texas Comp Engn Res Ctr Austin TX 78712 USA 

出 版 物：《IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS》 (IEEE Trans Parallel Distrib Syst)

年 卷 期：1999年第10卷第6期

页      面：627-641页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：control flow checking assertions fault injection coverage latency 

摘      要：This paper evaluates the concurrent error detection capabilities of system-level checks, using fault and error injection. The checks comprise application and system level mechanisms to detect control flow errors. We propose Enhanced Control-Flow Checking Using Assertions (ECCA). In ECCA, branch-free intervals (BFI) in a given high or intermediate level program are identified and the entry and exit points of the intervals are determined. BFIs are then grouped into blocks, the size of which is determined through a performance/overhead analysis. The blocks are then fortified with preinserted assertions. For the high level ECCA, we describe an implementation of ECCA through a preprocessor that will automatically insert the necessary assertions into the program. Then, we describe the intermediate implementation possible through modifications made on gee to make it ECCA capable. The fault detection capabilities of the checks are evaluated both analytically and experimentally. Fault injection experiments are conducted using FERRARI [1] to determine the fault coverage of the proposed techniques.