Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems

作     者：Zhao, Peiyi McNeely, Jason B. Golconda, Pradeep K. Venigalla, Soujanya Wang, Nan Bayoumi, Magdy A. Kuang, Weidong Downey, Luke 

作者机构：Chapman Univ Dept Math & Comp Sci Integrated Circuit Design & Embedded Syst Lab Orange CA 92604 USA Univ Louisiana Lafayette Ctr Adv Comp Studies Lafayette LA 70504 USA W Virginia Univ Dept Elect & Comp Engn Inst Technol Montgomery WV 25136 USA Intel Corp Folsom CA 95630 USA Univ Texas Pan Amer Dept Elect Engn Edinburg TX 78539 USA 

出 版 物：《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 (IEEE Trans Very Large Scale Integr VLSI Syst)

年 卷 期：2009年第17卷第9期

页      面：1196-1202页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Broadcom, Inc Emulex, Inc U.S. Department of Energy (DoE) EETAPP program [DE97ER12220] Governor's Information Technology Initiative 

主　　题：Dual supply flip-flop level conversion low power 

摘      要：Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different level-shifting schemes are analyzed and classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor style, and precharged style. An efficient level-shifting scheme, the clocked-pseudo-NMOS (CPN) level conversion scheme, is presented. One novel level conversion flip-flop (CPN-LCFF) is proposed, which combines the conditional discharge technique and pseudo-NMOS technique. In view of power and delay, the new CPN-LCFF outperforms previous LCFF by over 8% and 15.6%, respectively.