"It's a small world after all": NoC performance optimization via long-range link insertion

作     者：Ogras, Umit Y. Marculescu, Radu 

作者机构：Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA 

出 版 物：《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 

年 卷 期：2006年第14卷第7期

页      面：693-706页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：design automation multiprocessor system-on-chip (MP-SoC) network-on-chip (NoC) performance analysis 

摘      要：Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental, results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.