hbtSOTLearner: A Hierarchical-Backtracking-Based Parameter Learner for Small Outline Transistor

作     者：Sun, Hao Yu, Jinyong Liu, Weihua Yang, Xianqiang 

作者机构：Harbin Inst Technol Res Inst Intelligent Control & Syst Harbin 150001 Heilongjiang Peoples R China 

出 版 物：《IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS》 (IEEE工业电子学汇刊)

年 卷 期：2019年第66卷第12期

页      面：9789-9797页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0804[工学-仪器科学与技术] 0811[工学-控制科学与工程] 

基　　金：111 Project [B16014] Key Laboratory of Micro-systems and Micro-structures Manufacturing of Ministry of Education [2017 KM008] State Key Laboratory of Robotics and Systems of Harbin Institute of Technology 

主　　题：Image segmentation parameter learning algorithm small outline transistor (SOT) package surface mount technology (SMT) two-stage hierarchical backtracking algorithm 

摘      要：This paper is concerned with parameter learning of chips with small outline transistor (SOT) package, which is one of the most widely used package in surface mount technology (SMT) and has various subcategories. Previously learned parameter is crucial to most SOT-related industrial applications, such as location and defect inspection. However, parameter learning is a challenging work because of package diversity and image-quality deterioration in practical industrial applications. The conventional methods, checking data sheet or manual measuring, cannot meet the accuracy requirement of SMT. This paper proposes a hierarchical-backtracking-based parameter learner for SOT chips. The Gaussian mixture model based clustering algorithm and random walker algorithm are firstly applied to extracting lead regions of SOT chip;Then, chip models are inferred by grouping these lead regions with a hierarchical backtracking algorithm. Finally, redundant models are eliminated with root set pyramids and the valid chip model is obtained. The experimental results show that the proposed parameter learner performs well on SOT chips and is robust to noisy sets.