A large-scale nesting ring multi-chip architecture for manycore processor systems

作     者：Li, Wenzhe Guo, Bingli Li, Xin Zhou, Yu Huang, Shanguo Rouskas, George N. 

作者机构：Beijing Univ Posts & Telecommun State Key Lab Informat Photon & Opt Commun Beijing Peoples R China North Carolina State Univ Dept Comp Sci Raleigh NC USA 

出 版 物：《OPTICAL SWITCHING AND NETWORKING》 (光开关和网络：计算机网络杂志)

年 卷 期：2019年第31卷

页      面：183-192页

核心收录：

学科分类：0810[工学-信息与通信工程] 0711[理学-系统科学] 07[理学] 08[工学] 070105[理学-运筹学与控制论] 081101[工学-控制理论与控制工程] 0701[理学-数学] 071101[理学-系统理论] 0811[工学-控制科学与工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 0702[理学-物理学] 

基　　金：NSF of China [61601054, 1331008, 61701039, 61571058, 61771074] Project of China Scholarship Council NSF for Outstanding Youth Scholars of China Youth Research and Innovation Program of BUPT, State Key Lab. of Adv. Optical Commun. Systems Networks 

主　　题：ONoC Large-scale Routing algorithm Resource reservation 

摘      要：The optical network on chip (ONoC) paradigm has emerged as a promising solution to multi-core/many-core processor systems for offering enormous bandwidth and low power consumption. As chip multiprocessors (CMPs) scale to unprecedented numbers of cores, the performance of next-generation CMPs will be bounded by the process yield and power density of single chip. In earlier work we proposed a multi-chip ONoC architecture that scales to large numbers of CMPs and delivers high performance in terms of delay and throughout. Building on that work, in this paper we propose an optimized architecture for integrating a large number of cores into chips with a novel control strategy, including a contention resolution scheme and a resource reservation scheme. The proposed control strategy is crucial to large scale ONoCs, because the resource reservation scheme ensures efficient wavelength allocation for the traffic while the contention management scheme is effective in reducing the impact of contentions. To sustain good performance and energy efficiency of large-scale ONoC, the topology is optimized to reduce the average transmission distance with minimum increase of power consumption. We evaluate the proposed architecture within a 1000-core processor system and compare it with CMesh and several previously proposed topologies with different control strategies. The simulation results show that, our new large-scale architecture can achieve better performance on throughput and delay.