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Implementation of a RISC microprocessor for programmable logic controllers

为可编程逻辑控制器的 RISC 的实现

作     者:Rho, GS Koo, KH Chang, N Park, J Kim, YG Kwon, WH 

作者机构:SAMSUNG AEROSP IND LTDKYONGGI DO 441600SOUTH KOREA 

出 版 物:《MICROPROCESSORS AND MICROSYSTEMS》 (微处理机与微型系统)

年 卷 期:1995年第19卷第10期

页      面:599-608页

核心收录:

学科分类:0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术(可授工学、理学学位)] 

主  题:programmable logic controllers RISC architecture special purpose microprocessor 

摘      要:A special purpose RISC (reduced instruction set computer) microprocessor for programmable logic controllers (PLC), named PLCRISC, is proposed. To develop an optimal PLCRISC, we analysed existing PLC programs currently used in factories, with special attention to the instruction execution characteristics and features required for a high performance PLC processor. Based on this analysis, an optimal RISC-style instruction set and an architecture suitable for the required features are suggested. In particular, the instruction format, the instruction pipeline, and the detailed internal architecture are the significant characteristics of the proposed PLCRISC. The performance enhancement achieved with a PLCRISC is seen from a straightforward evaluation. ASIC implementation with VHDL is also discussed. The PLCRISC is under fabrication in a 0.8 mu m CMOS technology.

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