Scheduling with multiple voltages

作     者：Raje, S Sarrafzadeh, M 

作者机构：Northwestern Univ Dept Elect Engn & Comp Sci Evanston IL 60208 USA 

出 版 物：《INTEGRATION-THE VLSI JOURNAL》 (集成；超大规模集成电路杂志)

年 卷 期：1997年第23卷第1期

页      面：37-59页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Russian Science Foundation, RSF, (MIP-9207267) Russian Science Foundation, RSF 

主　　题：data flow graph scheduling behavioral synthesis low-power design multiple voltages 

摘      要：This paper presents a low power design technique at the behavioral synthesis stage. A scheduling technique for low power is studied and a theoretical foundation is established. The equation for dynamic power, P-dyn=V(dd)(2)C(load)f(switch), is used as a basis. The voltage applied to the functional units is varied, slowing down the functional unit throughput and reducing the power while meeting the throughput constraint for the entire system. The input to our problem is an unscheduled data flow graph with a timing constraint. The goal is to establish a voltage value at which each of the operations of the data flow graph would be performed, thereby fixing the latency for the operation such that the total timing constraint for the system is met. We give an algorithm to minimize the system s power;the algorithm finds an optimal schedule. The timing constraint for our system could be any value greater than or equal to the critical path. The experimental results for some high-level synthesis benchmarks show considerable reduction in the power consumption. Using 5 and 3 V supply voltages we achieve a maximum reduction of approximately 40% given tight timing constraints. Similarly, we obtain a 46% reduction using 5, 3 and 2.4 V supply voltages. For larger timing constraints, the maximum reduction is about 64% using 5 and 3 V supply voltages and a maximum reduction of about 74% using 5, 3 and 2.4 V supply voltages.