A 0.23 pJ 11.05-bit ENOB 125-MS/s pipelined ADC in a 0.18 μm CMOS process

作     者：王勇 张剑云 尹睿 赵宇航 张卫 

作者机构：State Key Laboratory of ASIC & SystemSchool of MicroelectronicsFudan University Shanghai Integrated Circuit Research and Development Center Co.Ltd. 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2015年第36卷第5期

页      面：170-174页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0803[工学-光学工程] 

基　　金：Project supported by the Foundation of Shanghai Municipal Commission of Economy and Informatization(No.130311) 

主　　题：analog-to-digital converter sample-and-hold Nyquist rate input frequency 

摘      要：This paper describes a 12-bit 125-MS/spipelinedanalog-to-digitalconverter（ADC）thatisimplemented in a 0.18 #m CMOS process. A gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.79 least significant bit （LSB） and 0.86 LSB, respectively, at the full sampling rate. The ADC exhibits an effective number of bits （ENOB） of more than 11.05 bits at the input frequency of 10.5 MHz. The ADC also achieves a 10.5 bits ENOB with the Nyquist input frequency at the full sample rate. In addition, the ADC consumes 62 mW from a 1.9 V power supply and occupies 1.17 mm2, which includes an on-chip reference buffer. The figure-of-merit of this ADC is 0.23 p J/step.