Focal-Plane Sensing-Processing: A Power-Efficient Approach for the Implementation of Privacy-Aware Networked Visual Sensors

作     者：Fernandez-Berni, Jorge Carmona-Galan, Ricardo del Rio, Rocio Kleihorst, Richard Philips, Wilfried Rodriguez-Vazquez, Angel 

作者机构：CSIC Univ Sevilla Inst Microelect Seville IMSE CNM Seville 41092 Spain Ghent Univ IMinds TELIN IPI B-9000 Ghent Belgium 

出 版 物：《SENSORS》 (传感器)

年 卷 期：2014年第14卷第8期

页      面：15203-15226页

核心收录：

学科分类：0710[理学-生物学] 071010[理学-生物化学与分子生物学] 0808[工学-电气工程] 07[理学] 0804[工学-仪器科学与技术] 0703[理学-化学] 

基　　金：Spanish Government [TEC2012-38921-C02] MINECO, MINisterio de Economia y COmpetitividad (European Region Development Fund, ERDF/FEDER) MINECO [IPT-2011-1625-430000] CDTI, Centro para el Desarrollo Tecnologico Industrial (ERDF/FEDER) [IPC-20111009] Junta de Andalucia, Consejeria de Economia, Innovacion, Ciencia y Empleo [TIC 2338-2013 CEICE] Office of Naval Research (USA) [N000141410355] Faculty of Engineering of Ghent University 

主　　题：visual sensor networks Internet of Things (IoT) privacy security vision sensor focal-plane processing obfuscation pixelation granular space feature extraction 

摘      要：The capture, processing and distribution of visual information is one of the major challenges for the paradigm of the Internet of Things. Privacy emerges as a fundamental barrier to overcome. The idea of networked image sensors pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. Power consumption also constitutes a crucial aspect. Images contain a massive amount of data to be processed under strict timing requirements, demanding high-performance vision systems. In this paper, we describe a hardware-based strategy to concurrently address these two key issues. By conveying processing capabilities to the focal plane in addition to sensing, we can implement privacy protection measures just at the point where sensitive data are generated. Furthermore, such measures can be tailored for efficiently reducing the computational load of subsequent processing stages. As a proof of concept, a full-custom QVGA vision sensor chip is presented. It incorporates a mixed-signal focal-plane sensing-processing array providing programmable pixelation of multiple image regions in parallel. In addition to this functionality, the sensor exploits reconfigurability to implement other processing primitives, namely block-wise dynamic range adaptation, integral image computation and multi-resolution filtering. The proposed circuitry is also suitable to build a granular space, becoming the raw material for subsequent feature extraction and recognition of categorized objects.