Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

作     者：Huang, Chi-Ray Chiou, Lih-Yih 

作者机构：Natl Cheng Kung Univ Dept Elect Engn Tainan Taiwan 

出 版 物：《IET CIRCUITS DEVICES & SYSTEMS》 (IET Circuits Devices Syst.)

年 卷 期：2018年第12卷第6期

页      面：713-719页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

基　　金：Ministry of Science and Technology Ministry of Science and Technology in Taiwan [MOST 105-2218-E-006-024, MOST 106-2221-E-006-239] 

主　　题：CMOS integrated circuits SRAM chips low-power electronics integrated circuit design control engineering computing asynchronous machines machine control asynchronous dual word-line control bit-interleaved ultra-low voltage operation random-access memory cell write-ability read stability ultra-low voltage single bit-line 8T SRAM cell ingle-ended 8T bit-cell dual word-line control half-select stability metal-oxide-semiconductor process 

摘      要：This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues;nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4kb test chip was implemented in a 90nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360mV with 2.68W power consumption.