Rapid transient fault insertion in large digital systems

作     者：Rohani, Alireza Kerkhoff, Hans G. 

作者机构：Univ Twente CTIT Testable Design & Test Integrated Syst Grp NL-7500 AE Enschede Netherlands 

出 版 物：《MICROPROCESSORS AND MICROSYSTEMS》 (微处理机与微型系统)

年 卷 期：2013年第37卷第2期

页      面：147-154页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Agentschap NL [CT302] 

主　　题：Component Failure analysis Fault modeling and simulation Transient faults 

摘      要：This paper presents a technique for rapid transient fault injection, regarding the CPU time, to perform simulation-based fault-injection in complex System-on-Chip Systems (SoCs). The proposed approach can be applied to complex circuits, as it is not required to modify the top-level modules of a design;moreover, it is capable to inject a wide range of fault models in a design and finally a competitive reduction in terms of CPU time will be achieved. The root of our method is based on the usage of simulator-commands along with partial code modification techniques. To prove the efficiency of the proposed method, it has been implemented on two case studies, a pre-synthesized netlist of an AVR microcontroller from ATMEL and a post placed-and-routed Verilog netlist of a high performance reconfigurable processor in 90-nm UMC technology, Xentium processor from Recore Systems. Experimental results show that our technique is able to reduce the CPU time by a factor ranging from 27% to 67% compared with typical simulation-based fault-injection approaches and by a factor of 10% compared with rapid simulation-based techniques. (C) 2012 Elsevier B.V. All rights reserved.